SL811HS
4.4
Data Port, Microprocessor Interface
The SL811HS microprocessor interface provides an 8-bit bidirectional data path along with appropriate control lines to interface
to external processors or controllers. The control lines, Chip Select, Read and Write input strobes and a single address line, A0,
along with the 8-bit data bus, support programmed I/O or memory mapped I/O designs.
Access to memory and control register space is a simple two step process, requiring an address Write with A0 set = “0,” followed
by a register/memory Read or Write cycle with address line A0 set = “1.”
In addition, DMA bidirectional interface in slave mode is available with handshake signals such as DREQ, ACK, WR, RD, CS and
INTR. Please refer to the SL811S spec.
The SL811HS Write or Read operation terminates when either nWR or nCS goes inactive. For devices interfacing to the SL811HS,
that deactivate the Chip Select nCS before the Write nWR, the data hold timing should be measured from the nCS and will be
the same value as specified. Thus, both Intel− and Motorola-type CPUs can work easily with the SL811HS without any external
glue logic requirements.
4.5
Interrupt Controller
The SL811HS interrupt controller provides a single output signal (INTRQ) that can be activated by a number of events that may
occur as result of USB activity. Control and status registers are provided to allow the user to select single or multiple events,
which will generate an interrupt (assert INTRQ), and lets the user view interrupt status. The interrupts can be cleared by writing
to the appropriate register (the Status Register at address 0x0d).
4.6
Buffer Memory
The SL811HS contains 256 bytes of internal buffer memory. The first 16 bytes of memory represent control and status registers
for programmed I/O operations. The remaining memory locations are used for data buffering (max. 240 Bytes).
Access to the registers and data memory is through an external microprocessor, 8-bit data bus, in either of two addressing modes,
indexed or, if used with multiplexed address/data bus interfaces, direct access. With indexed addressing, the address is first
written to the device with the A0 address line LOW, then the following cycle with A0 address line HIGH is directed to the specified
address. USB transactions are automatically routed to the memory buffer. Control registers are provided, so that pointers and
block sizes in buffer memory can be can set up.
4.6.1
Auto Address Increment Mode
The SL811HS supports auto-increment mode for Read or Write Cycles, A0 mode. In A0 mode, the Micro Controller sets up the
address only once. On any subsequent DATA Read or Write access, the internal address pointer will advance to the next DATA
location.
4.6.1.1 For example
Write 0x10 to SL811HS in address cycle (A0 is set LOW)
Write 0x55 to SL811HS in data cycle (A0 is set HIGH) -> Write 0x55 to location 0x10
Write 0xaa to SL811HS in data cycle (A0 is set HIGH) -> Write 0xaa to location 0x11
Write 0xbb to SL811HS in data cycle (A0 is set HIGH) -> Write 0xbb to location 0x12
The advantage of auto address increment mode is that it reduces the number of SL811HS memory Read/Write cycles required
to move data to/from the device. For example, transferring 64-bytes of data to/from SL811HS using auto increment mode, will
reduce the number of cycles to 1 Address Write and 64 Read/Write Data cycles, compared to 64 Address Writes and 64 Data
Cycles for Random Access.
4.7
PLL Clock Generator
Either a 12-MHz or a 48-MHz external crystal can be used with the SL811HS. Two pins, X1 and X2, are provided to connect a
low-cost crystal circuit to the device as shown in
Figure 4-2
and
Figure 4-3.
If an external 48-MHz clock source is available in the
application, it can be used instead of the crystal circuit by connecting the source directly to the X1 input pin. When a clock is used,
the X2 pin is left unconnected.
Document #: 38-08008 Rev. *A
Page 6 of 29
CYPRESS [ CYPRESS SEMICONDUCTOR ]
