SL811HS
Bus Interface Timing Requirements
I/O Write Cycle
twrhigh
twr
nWR
twasu
A0
twahld
twdhld
twdsu
twdsu
twdhld
Register or Memory
Address
DATA
D0-D7
twshld
twcsu
nCS
Tcscs See Note.
I/O Write Cycle to Register or Memory Buffer
Parameter
Description
Write pulse width
Min
85 ns
0 ns
0 ns
Typ
Max
tWR
tWCSU
Chip select set-up to nWR LOW
tWSHLD
Chip select hold time
After nWR HIGH
tWASU
A0 address set-up time
A0 address hold time
85 ns
10 ns
85 ns
5 ns
tWAHLD
tWDSU
tWDHLD
tCSCS
Data to Write HIGH set-up time
Data hold time after Write HIGH
nCS inactive to nCS* asserted
NWR HIGH
85 ns
85 ns
tWRHIGH
Note nCS an be held LOW for multiple Write cycles provided nWR is cycled. Write Cycle Time for Auto Inc Mode Writes is 170 ns
minimum.
Document 38-08008 Rev. *F
Page 25 of 32
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