SL811HS
DMA Write Cycle
tackrq
tdakrq
nDRQ
tdack
nDACK
tdwrlo
D0-D7
nWR
DATA
tdsu
tdwrp
tdhld
tackwrh
DMA Write Cycle
SL811 DMA WRITE CYCLE TIMING
Parameter
tdack
Description
Min
80 ns
5 ns
Typ
Max
nDACK low
tdwrlo
nDACK to nWR low delay
nDACK low to nDRQ high delay
nWR pulse width
tdakrq
5 ns
tdwrp
65 ns
5 ns
tdhld
Data hold after nWR high
Data set-up to nWR strobe low
NDACK high to nDRQ low
NDACK high to nDRQ low
DMA Write Cycle Time
tdsu
60 ns
5 ns
tackrq
tackwrh
twrcycle
5 ns
150 ns
Note nWR must go low after nDACK goes low in order for nDRQ to clear. If this sequence is not implemented as requested, the next
nDRQ is not inserted.
Document 38-08008 Rev. *F
Page 27 of 32
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