SL811HS
I/O Read Cycle
twr
twrrdl
nWR
A0
twasu
twahld
trdp
nRD
D0-D7
nCS
tracc
trdhld
trshld
twdsu
twdhld
Register or Memory
Address
DATA
trcsu
Tcscs *Note
I/O Read Cycle from Register or Memory Buffer
Parameter
Description
Min
85 ns
85 ns
0 ns
Typ
Max
tWR
Write pulse width
Read pulse width
tRD
tWCSU
tWASU
tWAHLD
tWDSU
tWDHLD
tRACC
tRDHLD
tRCSU
tRSHLD
Chip select set-up to nWR
A0 address set-up time
85 ns
10 ns
85 ns
5 ns
A0 address hold time
Data to Write HIGH set-up time
Data hold time after Write HIGH
Data valid after Read LOW
Data hold after Read HIGH
Chip select LOW to Read LOW
NCS hold after Read HIGH
nCS inactive to nCS *asserted
nWR HIGH to nRD LOW
25 ns
40 ns
0 ns
85 ns
0 ns
TCSCS
*
85 ns
85ns
tWRRDL
Note nCS can be kept LOW during multiple Read cycles provided nRD is cycled. Rd Cycle Time for Auto Inc Mode Reads is 170 ns
minimum.
Document 38-08008 Rev. *F
Page 26 of 32
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