SL811HS
DMA Read Cycle
nDRQ
tdckdr
tdakrq
tdack
nDACK
D0-D7
tddrdlo
DATA
tdaccs
tdhld
tdrdp
nRD
SL811 DMA Read Cycle Timing
SL811 DMA READ CYCLE TIMING
Parameter
Description
Min
100 ns
0 ns
Typ
Max
tdack
nDACK low
tddrdlo
tdckdr
tdrdp
nDACK to nRD low delay
nDACK low to nDRQ high delay
nRD pulse width
5 ns
90 ns
5 ns
tdhld
Date hold after nDACK high
Data access from nDACK low
nRD high to nDACK high
nDRQ low after nDACK high
DMA Read Cycle Time
tddaccs
tdrdack
tdakrq
trdcycle
85 ns
0 ns
5 ns
150 ns
Note Data is held until nDACK goes high regardless of state of nREAD.
Reset Timing
treset
nRST
tioact
nRD or nWR
Reset Timing
Parameter
tRESET
tIOACT
Description
nRst Pulse width
nRst HIGH to nRD or nWR active
Min
Typ
Max
16 clocks
16 clocks
Note Clock is 48 MHz nominal.
Document 38-08008 Rev. *F
Page 28 of 32
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