SL811HS
Table 34. Pin and Signal Description for Pins
48-Pin TQFP
Pin Type
Pin Name
Pin Description
AXC Pin No.
33
34
BIDIR
NC
D6
NC
Data 6. Microprocessor Data/Address Bus.
No connection.
35
NC
NC
No connection.
36
NC
NC
No connection.
37
NC
NC
No connection.
38
NC
NC
No connection.
39
BIDIR
IN
D7
Data 7. Microprocessor Data/Address Bus.
Master/Slave Mode Select. ’1’ selects Slave. ’0’ = Master.
Device VDD Power.
40
M/S
+3.3 VDC
A0
41
42[8]
VDD
IN
A0 = ’0’. Selects address pointer. Register A0 = ’1’. Selects data buffer or
register.
43
44
45
IN
OUT
IN
nDACK
nDRQ
nRD
DMA Acknowledge. An active LOW input used to interface to an external
DMA controller. DMA is enabled only in slave mode. In host mode, the pin
should be tied HIGH (logic ’1’).
DMA Request. An active LOW output used with an external DMA controller.
nDRQ and nDACK form the handshake for DMA data transfers. In host
mode, leave the pin unconnected.
Read Strobe Input. An active LOW input used with nCS to read
registers/data memory.
46
47
48
NC
NC
NC
NC
NC
NC
No connection.
No connection.
No connection.
Figure 6. Package Markings (48-Pin TQFP)
Part Number
YYWW-X.X
XXXX
YYWW = Date code
XXXX = Product code
X.X = Silicon revision number
Notes
7. VDD can be derived from the USB supply. Figure 5 on page 20 shows a simple method to provide 3.3 V/30 mA. Another option is to use a Torex Semiconductor,
Ltd. 3.3 V SMD regulator (part number XC62HR3302MR).
8. The A0 Address bit is used to access address register or data registers in I/O Mapped or Memory Mapped applications.
Document 38-08008 Rev. *F
Page 22 of 32
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