CY8C27x43 Final Data Sheet
3. Electrical Specifications
PLL
Enable
T
24 MHz
PLLSLEWLOW
FPLL
PLL
Gain
1
Figure 3-4. PLL Lock for Low Gain Setting Timing Diagram
32K
Select
32 kHz
T
OS
F32K2
Figure 3-5. External Crystal Oscillator Startup Timing Diagram
Jitter24M1
F24M
Figure 3-6. 24 MHz Period Jitter (IMO) Timing Diagram
Jitter32k
F32K2
Figure 3-7. 32 kHz Period Jitter (ECO) Timing Diagram
August 3, 2004
Document No. 38-12012 Rev. *I
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