This part is not recommended for new designs
Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI
Bridge for new designs
CY7C68300A
Pin Descriptions
(continued)
SSOP QFN
Pin
Pin Pin Name
46
47
48
49
39
40
41
42
VBUS_PW
R_VALID
ARESET#
GND
RESET#
Pin
Type
I
O/Z
GND
I
Default State at Start-up
Input
Pin Description
VBUS detection.
Indicates to the CY7C68300A that VBUS
power is present.
ATA Reset.
Ground.
Active LOW Reset.
Resets the entire chip. This pin is normally
tied to VCC through a 100K resistor, and to GND through a
0.1-µF capacitor, supplying a 10-ms reset.
V
CC
. Connect to 3.3V power source.
Input – If CY7C68300A is not
in mfg mode, polled every 20
ms after start-up. If LOW,
SSOP pins 36–38, 41–45
and 47 or QFN pins 29–31,
34–38 and 40 are three-
stated.
Active HIGH.
ATA interface enable. Allows ATA bus sharing
with other host devices. Setting ATA_EN = 1 enables the ATA
interface for normal operation. Disabling ATA_EN three-states
(High-Z) the ATA interface and halts the ATA interface state
machine logic.
50
51
43
44
V
CC
ATA_EN
PWR
I
52
53
54
55
56
45
46
47
48
49
DD8
DD9
DD10
DD11
DD12
I/O
Hi-Z
I/O
Hi-Z
I/O
Hi-Z
I/O
Hi-Z
I/O
Hi-Z
ATA Data bit 8.
ATA Data bit 9.
ATA Data bit 10.
ATA Data bit 11.
ATA Data bit 12.
3.2
3.2.1
Additional Pin Descriptions
DPLUS, DMINUS
20pF
24MHz crystal
DPLUS and DMINUS are the USB signaling pins, and they
should be tied to the D+ and D– pins of the USB connector.
Because they operate at high frequencies, the USB signals
require special consideration when designing the layout of the
PCB.
3.2.2
SCL, SDA
20pF
The clock and data pins for the I
2
C-compatible port should be
connected to your configuration EEPROM and to V
CC
through
2.2k resistors.
3.2.3
XTALIN, XTALOUT
Figure 3-3. XTALIN, XTALOUT Diagram
ATA_EN signal could be detected properly under all circum-
stances. The CY7C68300A will behave in the following
manner:
• If ATA_EN transitions to '0' during normal operation, the
CY7C68300A will disconnect from the USB and drop to a
low-power mode.
• If ATA_EN transitions to '1' when in low-power mode and
no other condition is causing the low-power state, the
CY7C68300A will return to a post-reset state and reconnect
to the USB.
• If the CY7C68300A is already in suspend and ATA_EN
transitions to '0', the CY7C68300A will resume only long
enough to stop driving the ATA interface (High-Z) and drop
back to low-power again.
• If the CY7C68300A is already in suspend and ATA_EN
transitions to '1', the CY7C68300A will resume only long
enough to start driving the ATA interface and drop to low-
power again.
The CY7C68300A requires a 24-MHz signal to derive internal
timing. Typically a 24-MHz parallel-resonant fundamental
mode crystal is used, but a 24-MHz square wave from another
source can also be used. If a crystal is used, connect the pins
to XTALIN and XTALOUT, and also through 20-pF capacitors
to GND. If an alternate clock source is used, apply it to XTALIN
and leave XTALOUT open.
3.2.4
ATA_EN
ATA_EN allows bus sharing with other host devices. Setting
ATA_EN = 1 enables the ATA interface for normal operation.
Setting ATA_EN = 0 disables (High-Z) the ATA interface pins
and removes the CY7C68300A from the USB. Because the
CY7C68300A supports a true low-power USB suspend state,
new functionality was added to ensure that transitions of the
Note:
2. A # sign after the signal name indicates that it is an active LOW signal.
Document #: 38-08031 Rev. *E
Page 5 of 21
CYPRESS [ CYPRESS SEMICONDUCTOR ]
