This part is not recommended for new designs
Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI
Bridge for new designs
CY7C68300A
and receives status and data from the CY7C68300A using
standard USB protocol.
The ATA/ATAPI port of the CY7C68300A is connected to a
mass storage device. A 4-Kbyte buffer maximizes ATA/ATAPI
data transfer rates by minimizing losses due to device seek
times. The ATA interface supports ATA PIO modes 0, 3, and 4,
and Ultra DMA modes 2 and 4.
The device initialization process is configurable, enabling the
CY7C68300A to initialize ATA/ATAPI devices without software
intervention.
3.0
3.1
Pin Assignments
Pin Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DD13
DD14
DD15
GND
NC
Vcc
GND
IORDY
DMARQ
AVcc
XTALOUT
XTALIN
AGND
Vcc
DPLUS
DMINUS
GND
Vcc
GND
PU10K
RESERVED
SCL
SDA
Vcc
DD0
DD1
DD2
DD3
DD12
DD11
DD10
DD9
DD8
ATA_EN
Vcc
RESET#
GND
ARESET#
VBUS_PWR_VALID
CS1#
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
EZ-USB AT2
CY7C68300A
56-pin SSOP
CS0#
DA2
DA1
DA0
INTRQ
Vcc
DMACK#
DIOR#
DIOW#
GND
Vcc
GND
DD7
DD6
DD5
DD4
Figure 3-1. 56-pin SSOP
Document #: 38-08031 Rev. *E
Page 2 of 21
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