This part is not recommended for new designs
Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI
Bridge for new designs
CY7C68300A
EZ-USB AT2™
USB 2.0 To ATA/ATAPI Bridge
1.0
Features
• Complies with USB-IF specifications for USB 2.0, the
USB
Mass Storage Class,
and the USB
Mass Storage
Class Bulk-Only Transport Specification
• Operates at high (480-Mbps) or full (12-Mbps) speed
• Complies with T13’s ATA/ATAPI-6 Draft Specification
• Supports 48-bit addressing for large hard drives
• Supports PIO modes 0, 3, 4, and UDMA modes 2, 4
• Uses one external serial EEPROM containing the USB
device serial number, vendor and product identification
data, and device configuration data
• ATA interface IRQ signal support
• Support for a single ATA/ATAPI device configured
either as master or slave
• “ATA-Enable” input signal, which three-states all
signals on the ATA interface in order to allow sharing
of the bus with another controller (e.g., an IEEE-1394 to
ATA bridge chip)
• Support for board-level manufacturing test via USB
interface
• 3.3V operation for self-powered devices
• 56-pin SSOP and 56-pin QFN packages
2.0
Introduction
The CY7C68300A implements a fixed-function bridge
between one USB port and one ATA- or ATAPI-based mass
storage device port. This bridge adheres to the
Mass Storage
Class Bulk-Only Transport Specification
and is intended for
self-powered devices.
The USB port of the CY7C68300A is connected to a host
computer directly or via the downstream port of a USB hub.
Host software issues commands and data to the CY7C68300A
SCL
RESET
I2C-Compatible
Bus Controller
SDA
24
MHz
XTAL
PLL
ATA_EN (ATA Interf ace 3-state)
AT2 Internal Logic
ATA Interf ace
ControlSignals
Control
ATA
16 Bit ATA Data
Interf ace
Logic
VBUS
D+
D-
USB 2.0 XCVR
CY Smart USB
FS/HS
Engine
4kBy teFIFO
Data
Figure 1-1. Block Diagram
Cypress Semiconductor Corporation
Document #: 38-08031 Rev. *E
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised September 15, 2005
CYPRESS [ CYPRESS SEMICONDUCTOR ]
