This part is not recommended for new designs
Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI
Bridge for new designs
CY7C68300A
The ATA_EN pin is sampled at a rate of 50 times per second
by the CY7C68300A internal logic. This pin should be set to a
HIGH at start-up. Note that disabling the ATA bus with the
ATA_EN pin during the middle of a data transfer will result in
data loss and can cause the operating system on the Host
computer to crash.
3.2.5
ATA Interface Pins
• High speed, with a signaling bit rate of 480 Mbits/sec.
CY7C68300A does not support the low-speed signaling rate
of 1.5 Mbits/sec.
5.2
ATA Interface
If a cable is used to connect the CY7C68300A to a UDMA
device, the cable must be an 80-pin cable as shown in the
ATA-6 spec, Annex A.
3.2.6
VBUS_PWR_VALID
VBUS_PWR_VALID indicates to the CY7C68300A that power
is present on VBUS. This pin is polled by the CY7C68300A at
start-up and then every 20ms thereafter. If this pin is ‘1’, the
1.5K pull-up is attached to D+. If this pin is ‘0’, the
CY7C68300A will release the pullup on D+ as required by the
USB specification.
3.2.7
RESET#
The ATA/ATAPI port on the CY7C68300A is compliant with the
Information Technology AT Attachment with Packet Interface
6 (ATA/ATAPI-6) Specification, T13/1410D Rev 3B. The
CY7C68300A supports ATAPI packet commands over USB.
Additionally, the CY7C68300A translates ATAPI SFF-8070i
commands to ATA commands for seamless integration of ATA
devices with generic
Mass Storage Class Bulk Only Transport
drivers.
6.0
Enumeration
Asserting RESET# for 10 ms will reset the entire chip. This pin
is normally tied to V
CC
through a 100k resistor, and to GND
through a 0.1-µF capacitor.
During the power-up sequence, internal logic checks the I
2
C-
compatible port for an EEPROM whose first two bytes are both
0x4D. If a valid signature is found, the CY7C68300A uses the
values stored in the EEPROM to configure the USB
descriptors for normal operation. If an invalid EEPROM
signature is read, or if no EEPROM is detected, the
CY7C68300A defaults into Board Manufacturing Test Mode.
The two modes of operation are described in subsections 6.1
and 6.2, below.
6.1
R8
100K
NRESET
C1
0.1 uFd
Board Manufacturing Test Mode
Figure 3-4. Typical Reset Circuit
In Board Manufacturing Test Mode, the chip behaves as a
USB 2.0 device but the ATA/ATAPI interface is not active. The
CY7C68300A allows for reading and writing an EEPROM and
for board level testing through vendor specific ATAPI
commands utilizing the CBW Command Block as described in
the USB
Mass Storage Class Bulk-Only Transport Specifi-
cation.
There is a vendor-specific ATAPI command for the
EEPROM access (CfgCB) and one for the board level testing
(MfgCB).
6.1.1
CfgCB
4.0
Applications
The CY7C68300A is a high-speed USB 2.0 peripheral device
that connects a single ATA or ATAPI storage device to a USB
host using the USB
Mass Storage Class
protocol.
4.1
Additional Resources
• CY4615 EZ-USB AT2 Reference Design Kit
• USB Specification version 2.0
• ATA Specification T13/1410D Rev 3B
• USB
Mass Storage Class Bulk Only Transport Specification,
http://www.usb.org/developers/data/devclass/
usbmassbulk_10.pdf.
The cfg_load and cfg_read vendor-specific commands are
passed down through the bulk pipe in the CBWCB portion of
the CBW. The format of this CfgCB is shown below. Byte 0 will
be a vendor-specific command designator whose value is
configurable and set in the configuration data (EEPROM
address 0x04). Byte 1 must be set to 0x26 to identify CfgCB.
Byte 2 is reserved and must be set to zero. Byte 3 is used to
determine the memory source to write/read. For the
CY7C68300A, this byte must be set to 0x02, meaning the
EEPROM. Bytes 4 and 5 will be used to determine the start
address. For the CY7C68300A, this must always be 0x0000.
Bytes 6 through 15 are reserved and should be set to zero.
The data transferred to the EEPROM must be in the format
specified in
of this data sheet. Maximum data
transfer size is 255 bytes.
The data transfer length is determined by the CBW Data
Transfer Length specified in bytes 8 through 11
(dCBWDataTransferLength) of the CBW. The type/direction of
the command will be determined by the direction bit specified
in byte 12, bit 7 (bmCBWFlags) of the CBW.
5.0
5.1
Functional Overview
USB Signaling Speed
CY7C68300A operates at two of the three rates defined in the
USB Specification Revision 2.0 dated April 27, 2000:
• Full speed, with a signaling bit rate of 12 Mbits/sec
Document #: 38-08031 Rev. *E
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