This part is not recommended for new designs
Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI
Bridge for new designs
CY7C68300A
Pin Descriptions
(continued)
SSOP QFN
Pin
Pin Pin Name
11
12
13
14
15
4
5
6
7
8
XTALOUT
XTALIN
AGND
V
CC
DPLUS
Pin
Type
Xtal
Xtal
GND
PWR
I/O
Default State at Start-up
Xtal
Xtal
Pin Description
24-MHz Crystal Output
(see section 3.2.3).
24-MHz Crystal Input
(see section 3.2.3).
Analog Ground.
Connect to ground with as short a path as
possible.
V
CC
. Connect to 3.3V power source.
Pulled high when Reset is
USB D+ Signal
(see section 3.2.1).
active. When Reset is
released, the pull-up is
controlled by pin 46(SSOP)/
39(QFN). When VBUS_
PWR_VALID is high, the line
is pulled up. VBUS_PWR
_VALID is polled at start-up
and then every 20 ms.
Hi-Z
USB D- Signal
(see section 3.2.1).
Ground.
V
CC
. Connect to 3.3V power source.
Ground.
Hi-Z
Tied to 10k ± 5% pull-up resistor.
Reserved.
Tie to GND.
O
I/O
PWR
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
PWR
GND
O/Z
O/Z
PWR
Input
Driven high (CMOS)
Driven high (CMOS)
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SCL/SDA will be active for
Clock signal for I
2
C-compatible interface
(see section
several ms at start-up. Then 3.2.2).
driven high.
Data signal for I
2
C-compatible interface
(see section 3.2.2).
V
CC
. Connect to 3.3V power source.
ATA Data bit 0.
ATA Data bit 1.
ATA Data bit 2.
ATA Data bit 3.
ATA Data bit 4.
ATA Data bit 5.
ATA Data bit 6.
ATA Data bit 7.
Ground.
V
CC
. Connect to 3.3V power source.
Ground.
ATA Control.
ATA Control.
ATA Control.
V
CC
. Connect to 3.3V power source.
IDE ATA Interrupt request.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
DMINUS
GND
V
CC
GND
PU10K
RESERVE
D
SCL
SDA
V
CC
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
GND
V
CC
GND
DIOW#
DIOR#
DMACK#
V
CC
INTRQ
DA0
DA1
DA2
CS0#
CS1#
I/O
GND
PWR
GND
O/Z
Driven high (CMOS)
O/Z
Driven high after 2 ms delay
ATA Address.
O/Z
Driven high after 2 ms delay
ATA Address.
O/Z
Driven high after 2 ms delay
ATA Address.
O/Z
Driven high after 2 ms delay
ATA Chip Select.
O/Z
Driven high after 2 ms delay
ATA Chip Select.
Document #: 38-08031 Rev. *E
Page 4 of 21
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