This part is not recommended for new designs
Use CY7C68300B EZ-USB AT2LP™ USB2.0 to ATA/ATAPI
Bridge for new designs
CY7C68300A
6.3
EEPROM Organization
The contents of the 256-byte (2048-bit) two-wire serial
EEPROM are arranged as follows. The column labeled
“Required Contents” contains the values that must be used for
proper operation of the CY7C68300A. The column labeled
“Suggested Contents” contains suggested values for the bytes
that are defined by the manufacturer. Some values, such as
Table 6-6. EEPROM Organization
EEPROM
Address
Configuration
0x00
0x01
0x02
I
2
C-compatible memory
device signature (LSB)
I
2
C-compatible memory
device signature (MSB)
APM Value
LSB I
2
C-compatible memory device signature byte.
MSB I
2
C-compatible memory device signature byte.
ATA Device Automatic Power Management Value. If an
attached ATA device supports APM and this field contains
other than 0x00, the CY7C68300A will issue a
SET_FEATURES command to Enable APM with this value
during the drive initialization process. Setting APM Value to
0x00 disables this functionality. This value is ignored with
ATAPI devices.
Time in 128-ms granularity before the CY7C68300A stops
polling the ALT STAT register for reset complete and restarts
the reset process (0x80 = 16.4 seconds).
Value in the first byte of the CBW CB field that designates that
the CB is t o be decoded as vendor specific ATA commands
instead of the ATAPI command block. See section 5.0 for
more detail on how this byte is used.
Bits(7:4) Set to 0
Bit (3)
Enables a delay of up to 120 ms at each read of the DRQ bit
where the device data length does not match the host data
length. This allows the CY7C68300A to work with most
devices that incorrectly clear the BUSY bit before a valid
status is present.
Bit (2)
Determines if a short packet is sent prior to the STALL of an
IN endpoint. The USB
Mass Storage Class Bulk-Only Speci-
fication
allows a device to send a short or zero-length IN
packet prior to returning a STALL handshake for certain
cases. Certain host controller drivers may require a short
packet prior to STALL.
1 = Force a short packet before STALL.
0 = Don’t force a short packet before STALL.
Bit (1)
Determines if the CY7C68300A is to do a SRST reset during
drive initialization.
1 = Perform SRST during initialization.
0 = Don’t perform SRST during initialization.
Bit (0)
Skip ATA_NRESET assertion.
0 = Allow ARESET# assertion for all resets.
1 = Disable ARESET# assertion except for power-on reset
cycles.
0x4D
0x4D
0x00
Field Name
Field Description
Required Suggested
Contents Contents
the Vendor ID and device and device serial number, must be
customized to meet USB compliance. See section 6.1 for
details on how to use vendor-specific ATAPI commands to
read and program the EEPROM. The serial EEPROM must be
hard-wired to address 0x04. This means that A0 and A1 of the
serial EEPROM must be tied to ground and that A2 must be
tied to 3.3V.
0x03
ATA Initialization Timeout
0x80
0x04
ATA Command Designator
0x24
0x05
Reserved
BUSY Bit Delay
0x07
Short Packet Before Stall
SRST Enable
Skip Pin Reset
Notes:
3. At least one reset must be enabled. Do not set SRST to 0 and Skip Pin Reset to 1at the same time.
4. SRST Enable must be set in conjunction with Skip Pin Reset. Setting this bit causes the CY7C68300A to bypass ARESET# during initialization. All reset events
except a power-on reset utilize SRST as the drive mechanism.
Document #: 38-08031 Rev. *E
Page 9 of 21
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