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CY7C1350G-133AXC 参数 Datasheet PDF下载

CY7C1350G-133AXC图片预览
型号: CY7C1350G-133AXC
PDF下载: 下载PDF文件 查看货源
内容描述: 4兆位( 128K ×36 )流水线SRAM与NOBL ?架构 [4-Mbit (128K x 36) Pipelined SRAM with NoBL? Architecture]
分类和应用: 存储内存集成电路静态存储器时钟
文件页数/大小: 15 页 / 336 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY7C1350G
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature
..................................... −65°C
to +150°C
Ambient Temperature with
Power Applied..................................................
−55°C
to +125°C
Supply Voltage on V
DD
Relative to GND.........−0.5V to +4.6V
Supply Voltage on V
DDQ
Relative to GND
.......−0.5V
to +V
DD
DC Voltage Applied to Outputs
in tri-state
..................................................−0.5V
to V
DDQ
+ 0.5V
Range
Commercial
Industrial
DC Input Voltage
....................................... −0.5V
to V
DD
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA
Operating Range
Ambient
Temperature (T
A
)
0°C to +70°C
−40°C
to +85°C
V
DD
3.3V – 5%
+10%
V
DDQ
2.5V – 5%
to V
DD
Electrical Characteristics
Over the Operating Range
[10, 11]
Parameter
V
DD
V
DDQ
V
OH
V
OL
V
IH
V
IL
I
X
Description
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
for 3.3V I/O, I
OH
=
−4.0
mA
for 2.5V I/O, I
OH
=
−1.0
mA
for 3.3V I/O, I
OL
= 8.0 mA
for 2.5V I/O, I
OL
=1.0 mA
Input HIGH Voltage
[10]
V
DDQ
= 3.3V
V
DDQ
= 2.5V
Input LOW
Voltage
[10]
V
DDQ
= 3.3V
V
DDQ
= 2.5V
Input Leakage Current GND
V
I
V
DDQ
except ZZ and MODE
Input Current of MODE Input = V
SS
Input = V
DD
Input Current of ZZ
I
OZ
I
DD
Output Leakage
Current
Input = V
SS
Input = V
DD
GND
V
I
V
DDQ,
Output Disabled
4-ns cycle, 250 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100MHz
I
SB1
Automatic CE
Power-Down
Current—TTL Inputs
V
DD
= Max, Device Deselected,
V
IN
V
IH
or V
IN
V
IL
f = f
MAX
= 1/t
CYC
4-ns cycle, 250 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
I
SB2
Automatic CE
Power-down
Current—CMOS
Inputs
V
DD
= Max, Device Deselected,
All speeds
V
IN
0.3V or V
IN
> V
DDQ
– 0.3V, f = 0
−5
–5
30
5
325
265
240
225
205
120
110
100
90
80
40
2.0
1.7
–0.3
–0.3
−5
−30
5
Test Conditions
Min.
3.135
2.375
2.4
2.0
0.4
0.4
V
DD
+ 0.3V
V
DD
+ 0.3V
0.8
0.7
5
Max.
3.6
V
DD
Unit
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
DD
Operating Supply V
DD
= Max., I
OUT
= 0 mA,
Current
f = f
MAX
= 1/t
CYC
Notes:
10. Overshoot: V
IH
(AC) < V
DD
+1.5V (Pulse width less than t
CYC
/2), undershoot: V
IL
(AC)> –2V (Pulse width less than t
CYC
/2).
11. T
Power-up
: Assumes a linear ramp from 0V to V
DD
(min.) within 200 ms. During this time V
IH
< V
DD
and V
DDQ
< V
DD.
Document #: 38-05524 Rev. *F
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