CY7C1350G
Switching Characteristics
Over the Operating Range
[17, 18]
–250
Parameter
t
POWER
Clock
t
CYC
t
CH
t
CL
t
CO
t
DOH
t
CLZ
t
CHZ
t
OEV
t
OELZ
t
OEHZ
Set-up Times
t
AS
t
ALS
t
WES
t
CENS
t
DS
t
CES
Hold Times
t
AH
t
ALH
t
WEH
t
CENH
t
DH
t
CEH
Address Hold After CLK Rise
ADV/LD Hold after CLK Rise
GW, BW
X
Hold After CLK Rise
CEN Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
0.3
0.3
0.3
0.3
0.3
0.3
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
Address Set-up Before CLK Rise
ADV/LD Set-up Before CLK Rise
GW, BW
X
Set-Up Before CLK Rise
CEN Set-up Before CLK Rise
Data Input Set-up Before CLK Rise
Chip Enable Set-Up Before CLK
Rise
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
ns
ns
ns
ns
ns
ns
Clock Cycle Time
Clock HIGH
Clock LOW
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z
[14, 15, 16]
–200
1
5.0
2.0
2.0
1
–166
Min.
Max.
1
–133
1
–100
ms
ns
ns
ns
4.5
1.5
0
ns
ns
ns
4.5
4.5
0
4.5
ns
ns
ns
ns
Description
V
DD
(typical) to the first Access
[13]
Min.
1
4.0
1.7
1.7
Max. Min. Max.
Min. Max. Min. Max. Unit
6.0
2.5
2.5
2.8
3.5
1.5
0
2.8
2.8
3.5
3.5
0
2.8
3.5
7.5
3.0
3.0
4.0
1.5
0
4.0
4.0
0
4.0
10
3.5
3.5
Output Times
2.6
1.0
0
2.6
2.6
0
2.6
0
1.0
0
Clock to High-Z
[14, 15, 16]
OE LOW to Output Valid
OE LOW to Output Low-Z
[14, 15, 16]
16]
OE HIGH to Output High-Z
[14, 15,
Notes:
13. This part has a voltage regulator internally; t
POWER
is the time that the power needs to be supplied above V
DD
minimum initially before a Read or Write operation
can be initiated.
14. t
CHZ
, t
CLZ
,t
OELZ
, and t
OEHZ
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
15. At any given voltage and temperature, t
OEHZ
is less than t
OELZ
and t
CHZ
is less than t
CLZ
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve tri-state prior to Low-Z under the same system conditions.
16. This parameter is sampled and not 100% tested.
17. Timing reference level is 1.5V when V
DDQ
= 3.3V and is 1.25V when V
DDQ
= 2.5V.
18. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05524 Rev. *F
Page 9 of 15
CYPRESS [ CYPRESS SEMICONDUCTOR ]
