CY7C1350G
Electrical Characteristics
Over the Operating Range
[10, 11]
(continued)
Parameter
I
SB3
Description
Automatic CE
Power-Down
Current—CMOS
Inputs
Test Conditions
V
DD
= Max, Device Deselected, or
V
IN
≤
0.3V or V
IN
> V
DDQ
– 0.3V
f = f
MAX
= 1/t
CYC
4-ns cycle, 250 MHz
5-ns cycle, 200 MHz
6-ns cycle, 166 MHz
7.5-ns cycle, 133 MHz
10-ns cycle, 100 MHz
I
SB4
Automatic CE
Power-Down
Current—TTL Inputs
V
DD
= Max, Device Deselected,
V
IN
≥
V
IH
or V
IN
≤
V
IL
, f = 0
All speeds
Min.
Max.
105
95
85
75
65
45
Unit
mA
mA
mA
mA
mA
mA
Capacitance
[12]
Parameter
C
IN
C
CLK
C
I/O
Description
Input Capacitance
Clock Input Capacitance
Input/Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
DD
= 3.3V, V
DDQ
= 3.3V
100 TQFP
Max.
5
5
5
119 BGA
Max.
5
5
7
Unit
pF
pF
pF
Thermal Resistance
[12]
Parameter
Θ
JA
Θ
JC
Description
Test Conditions
100 TQFP
Package
30.32
6.85
119 BGA
Package
34.1
14.0
Unit
°C/W
°C/W
Thermal Resistance (Junction to Test conditions follow standard
Ambient)
test methods and procedures for
Thermal Resistance (Junction to measuring thermal impedance,
per EIA/JESD51.
Case)
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT
Z
0
= 50Ω
R
L
= 50Ω
5 pF
R = 351Ω
3.3V
OUTPUT
R = 317Ω
ALL INPUT PULSES
V
DDQ
10%
GND
≤
1 ns
90%
90%
10%
≤
1 ns
V
T
= 1.5V
(a)
2.5V I/O Test Load
OUTPUT
Z
0
= 50Ω
R
L
= 50Ω
2.5V
INCLUDING
JIG AND
SCOPE
(b)
(c)
R = 1667Ω
V
DDQ
10%
5 pF
R =1538Ω
GND
≤
1 ns
ALL INPUT PULSES
90%
90%
10%
≤
1 ns
OUTPUT
V
T
= 1.25V
(a)
INCLUDING
JIG AND
SCOPE
(b)
(c)
Note:
12. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05524 Rev. *F
Page 8 of 15
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