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CY7C1350G-133AXC 参数 Datasheet PDF下载

CY7C1350G-133AXC图片预览
型号: CY7C1350G-133AXC
PDF下载: 下载PDF文件 查看货源
内容描述: 4兆位( 128K ×36 )流水线SRAM与NOBL ?架构 [4-Mbit (128K x 36) Pipelined SRAM with NoBL? Architecture]
分类和应用: 存储内存集成电路静态存储器时钟
文件页数/大小: 15 页 / 336 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY7C1350G
Switching Waveforms
Read/Write Timing
[19, 20, 21]
1
CLK
t
CENS
t
CENH
2
t CYC
3
4
5
6
7
8
9
10
t
CH
t
CL
CEN
t
CES
t
CEH
CE
ADV/LD
WE
BW
[A:D]
ADDRESS
t
AS
A1
t
AH
A2
t
DS
t
DH
A3
A4
t
CO
t
CLZ
t
DOH
A5
t
OEV
A6
t
CHZ
A7
Data
In-Out (DQ)
D(A1)
D(A2)
D(A2+1)
Q(A3)
Q(A4)
t
OEHZ
Q(A4+1)
D(A5)
Q(A6)
t
DOH
OE
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
BURST
READ
Q(A4+1)
WRITE
D(A5)
t
OELZ
READ
Q(A6)
WRITE
D(A7)
DESELECT
DON’T CARE
UNDEFINED
Notes:
19. For this waveform ZZ is tied LOW.
20. When CE is LOW, CE
1
is LOW, CE
2
is HIGH and CE
3
is LOW. When CE is HIGH, CE
1
is HIGH or CE
2
is LOW or CE
3
is HIGH.
21. Order of the Burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document #: 38-05524 Rev. *F
Page 10 of 15