CY7C145
CY7C144
Switching Characteristics
Over the Operating Range
[9]
(continued)
7C144-15
7C145-15
Parameter
WRITE CYCLE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE[11,12]
t
LZWE[11,12]
t
WDD[13]
t
DDD[13]
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold From Write
End
Address Set-Up to Write
Start
Write Pulse Width
Data Set-Up to Write End
Data Hold From Write End
R/W LOW to High Z
R/W HIGH to Low Z
Write Pulse to Data Delay
Write Data Valid to Read
Data Valid
BUSY LOW from Address
Match
BUSY HIGH from Address
Mismatch
BUSY LOW from CE LOW
BUSY HIGH from CE HIGH
Port Set-Up for Priority
R/W LOW after BUSY LOW
R/W HIGH after BUSY HIGH
BUSY HIGH to Data Valid
INT Set Time
INT Reset Time
SEM Flag Update Pulse (OE
or SEM)
SEM Flag Write to Read Time
SEM Flag Contention
Window
10
5
5
5
0
13
15
15
15
10
5
5
3
30
25
15
12
12
2
0
12
10
0
10
3
50
30
25
20
20
2
0
20
15
0
15
3
60
35
35
30
30
2
0
25
15
0
20
3
70
40
55
45
45
2
0
40
25
0
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C144-25
7C145-25
Min.
Max.
7C144-35
7C145-35
Min.
Max.
7C144-55
7C145-55
Min.
Max.
Unit
BUSY TIMING
[14]
t
BLA
t
BHA
t
BLC
t
BHC
t
PS
t
WB
t
WH
t
BDD
t
INS
t
INR
t
SOP
t
SWRD
t
SPS
15
15
15
15
5
0
20
25
25
25
15
5
5
20
20
20
20
5
0
30
35
25
25
20
5
5
20
20
20
20
5
0
30
55
35
35
30
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
INTERRUPT TIMING
[14]
SEMAPHORE TIMING
Notes:
13. For information on part-to-part delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform.
14. Test conditions used are Load 2.
7
CYPRESS [ CYPRESS SEMICONDUCTOR ]
