CY7C145
CY7C144
Switching Waveforms
(continued)
Write Cycle No. 1: OE Three-State Data I/Os (Either Port)
[21, 22, 23]
t
WC
ADDRESS
t
SCE
SEM OR CE
t
AW
R/W
t
SA
DATA IN
t
PWE
t
SD
DATA VALID
t
HD
t
HA
OE
t
HIGH IMPEDANCE
C144-13
t
HZOE
DATA OUT
LZOE
Write Cycle No. 2: R/W Three-State Data I/Os (Either Port)
[21, 23, 24]
t
WC
ADDRESS
t
SCE
SEM OR CE
t
SA
R/W
t
AW
t
PWE
t
HA
t
SD
DATA IN
t
HZWE
DATA OUT
DATAVALID
t
HD
t
LZWE
HIGH IMPEDANCE
C144-14
Notes:
21. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write, and either
signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates
the write.
22. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of t
PWE
or (t
HZWE
+ t
SD
) to allow the I/O drivers to turn off and
data to be placed on the bus for the required t
SD
. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply
and the write pulse can be as short as the specified t
PWE
.
23. R/W must be HIGH during all address transitions.
24. Data I/O pins enter high impedance when OE is held LOW during write.
9
CYPRESS [ CYPRESS SEMICONDUCTOR ]
