CY7C145
CY7C144
Switching Waveforms
(continued)
Semaphore Read After Write Timing, Either Side
[25]
t
AA
A
0
−A
2
VALID ADDRESS
t
AW
SEM
t
SCE
t
SD
I/O
0
t
SA
R/W
t
SWRD
OE
WRITE CYCLE
t
SOP
READ CYCLE
C144-15
t
OHA
VALID ADDRESS
t
ACE
t
SOP
t
HA
DATA
IN
VALID
t
PWE
t
HD
DATA
OUT
VALID
t
DOE
Semaphore Contention
[26, 27, 28]
A
0L
−A
2L
MATCH
R/W
L
SEM
L
t
SPS
A
0R
−A
2R
MATCH
R/W
R
SEM
R
C144-16
Notes:
25. CE = HIGH for the duration of the above timing (both write and read cycle).
26. I/O
0R
= I/O
0L
= LOW (request semaphore); CE
R
= CE
L
= HIGH
27. Semaphores are reset (available to both ports) at cycle start.
28. If t
SPS
is violated, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.
10
CYPRESS [ CYPRESS SEMICONDUCTOR ]
