CY7C145
CY7C144
Pin Configurations
(continued)
80-Pin TQFP
Top View
NC
I/O
2L
I/O
3L
I/O
4L
I/O
5L
GND
I/O
6L
I/O
7L
V
CC
NC
GND
I/O
0R
I/O
1R
I/O
2R
V
CC
I/O
3R
I/O
4R
I/O
5R
I/O
6R
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CY7C145
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
NC
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
BUSY
L
GND
M/S
BUSY
R
INT
R
A
0R
A
1R
A
2R
A
3R
A
4R
NC
NC
C144-4
Pin Definitions
Left Port
I/O
0L−7L(8L)
A
0L−12L
CE
L
OE
L
R/W
L
SEM
L
Right Port
I/O
0R−7R(8R)
A
0R−12R
CE
R
OE
R
R/W
R
SEM
R
Data bus Input/Output
Address Lines
Chip Enable
Output Enable
Read/Write Enable
Semaphore Enable. When asserted LOW, allows access to eight sema-
phores. The three least significant bits of the address lines will determine
which semaphore to write or read. The I/O
0
pin is used when writing to a
semaphore. Semaphores are requested by writing a 0 into the respective
location.
Interrupt Flag. INT
L
is set when right port writes location 1FFE and is
cleared when left port reads location 1FFE. INT
R
is set when left port writes
location 1FFF and is cleared when right port reads location 1FFF.
Busy Flag
Master or Slave Select
Power
Ground
Description
INT
L
INT
R
BUSY
L
M/S
V
CC
GND
BUSY
R
3
CYPRESS [ CYPRESS SEMICONDUCTOR ]
