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CY7C144-15AC 参数 Datasheet PDF下载

CY7C144-15AC图片预览
型号: CY7C144-15AC
PDF下载: 下载PDF文件 查看货源
内容描述: 8K X 8/9双口静态RAM与SEM , INT , BUSY [8K x 8/9 Dual-Port Static RAM with Sem, Int, Busy]
分类和应用: 存储内存集成电路静态存储器
文件页数/大小: 19 页 / 391 K
品牌: CYPRESS [ CYPRESS SEMICONDUCTOR ]
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CY7C145
CY7C144
AC Test Loads and Waveforms
5V
R1=893Ω
OUTPUT
C = 30 pF
R2=347Ω
OUTPUT
C=30pF
V
TH
=1.4V
(a) Normal Load (Load1)
C144-5
5V
R1=893Ω
OUTPUT
C = 5 pF
R2=347Ω
R
TH
=250Ω
(b) Thévenin Equivalent (Load 1)
C144-6
(c) Three-State Delay (Load 3)
C144-7
ALL INPUT PULSES
OUTPUT
C = 30 pF
3.0V
GND
10%
90%
90%
10%
3 ns
C144-9
3 ns
Load (Load 2)
C144-8
Switching Characteristics
Over the Operating Range
[9]
7C144-15
7C145-15
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE[10, 11,12]
t
LZCE[10, 11,12]
t
HZCE[10, 11,12]
t
PU[12]
t
PD[12]
Read Cycle Time
Address to Data Valid
Output Hold From Address
Change
CE LOW to Data Valid
OE LOW to Data Valid
OE Low to Low Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
0
15
3
10
3
10
0
25
3
15
0
35
3
15
10
3
15
3
20
0
55
15
15
3
25
15
3
20
3
25
25
25
3
35
20
3
25
35
35
3
55
25
55
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C144-25
7C145-25
Min.
Max.
7C144-35
7C145-35
Min.
Max.
7C144-55
7C145-55
Min.
Max.
Unit
t
HZOE[10, 11,12]
OE HIGH to High Z
Notes:
9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OI
/I
OH
and 30-pF load capacitance.
10. At any given temperature and voltage condition for any given device, t
HZCE
is less than t
LZCE
and t
HZOE
is less than t
LZOE
.
11. Test conditions used are Load 3.
12. This parameter is guaranteed but not tested.
6