CY7C145
CY7C144
Switching Waveforms
Read Cycle No. 1 (Either Port Address Access)
[15, 16]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
C144-10
Read Cycle No. 2 (Either Port CE/OE Access)
[15, 17, 18]
SEM or CE
OE
t
ACE
t
DOE
t
HZOE
t
HZCE
t
LZOE
t
LZCE
DATA OUT
t
PU
I
CC
I
SB
DATA VALID
t
PD
C144-11
Read Timing with Port-to-Port Delay (M/S=L)
[19, 20]
t
WC
ADDRESS
R
R/W
R
MATCH
t
PWE
t
SD
t
HD
DATAIN
R
VALID
ADDRESS
L
MATCH
t
DDD
DATA
OUTL
t
WDD
VALID
C144-12
Notes:
15. R/W is HIGH for read cycle.
16. Device is continuously selected CE = LOW and OE = LOW. This waveform cannot be used for semaphore reads.
17. Address valid prior to or coincident with CE transition LOW.
18. CE
L
= L, SEM = H when accessing RAM. CE = H, SEM = L when accessing semaphores.
19. BUSY = HIGH for the writing port.
20. CE
L
= CE
R
= LOW.
8
CYPRESS [ CYPRESS SEMICONDUCTOR ]
