1CY 7C14 4
fax id: 5205
CY7C145
CY7C144
8K x 8/9 Dual-Port Static RAM
with Sem, Int, Busy
Features
• True Dual-Ported memory cells which allow
simultaneous reads of the same memory location
• 8K x 8 organization (CY7C144)
• 8K x 9 organization (CY7C145)
• 0.65-micron CMOS for optimum speed/power
• High-speed access: 15ns
• Low operating power: I
CC
= 160 mA (max.)
• Fully asynchronous operation
• Automatic power-down
• TTL compatible
• Master/Slave select pin allows bus width expansion to
16/18 bits or more
• Busy arbitration scheme provided
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Available in 68-pin PLCC, 64-pin and 80-pin TQFP
• Pin compatible and functionally equivalent to
IDT7005/IDT7015
are included on the CY7C144/5 to handle situations when mul-
tiple processors access the same piece of data. Two ports are
provided permitting independent, asynchronous access for
reads and writes to any location in memory. The CY7C144/5
can be utilized as a standalone 64/72-Kbit dual-port static
RAM or multiple devices can be combined in order to function
as a 16/18-bit or wider master/slave dual-port static RAM. An
M/S pin is provided for implementing 16/18-bit or wider mem-
ory applications without the need for separate master and
slave devices or additional discrete logic. Application areas
include interprocessor/multiprocessor designs, communica-
tions status buffering, and dual-port video/graphics memory.
Each port has independent control pins: chip enable (CE),
read or write enable (R/W), and output enable (OE). Two flags,
BUSY and INT, are provided on each port. BUSY signals that the port
is trying to access the same location currently being accessed by the
other port. The interrupt flag (INT) permits communication between
ports or systems by means of a mail box. The semaphores are used
to pass a flag, or token, from one port to the other to indicate that a
shared resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared resource is
in use. An automatic power-down feature is controlled independently
on each port by a chip enable (CE) pin or SEM pin.
Functional Description
The CY7C144 and CY7C145 are high-speed CMOS 8K x 8
and 8K x 9 dual-port static RAMs. Various arbitration schemes
Logic Block Diagram
R/W
L
CE
L
OE
L
R/W
R
CE
R
OE
R
(7C145) I/O
8L
I/O
7L
I/O
0L
BUSY
L [1, 2]
A
12L
A
0L
ADDRESS
DECODER
I/O
CONTROL
I/O
CONTROL
I/O
8R
(7C145)
I/O
7R
I/O
0R
BUSY
R
A
12R
[1, 2]
MEMORY
ARRAY
ADDRESS
DECODER
A
0R
CE
L
OE
L
R/W
L
SEM
L
INT
L [2]
INTERRUPT
SEMAPHORE
ARBITRATION
CE
R
OE
R
R/W
R
SEM
R
INT
R [2]
M/S
C144-1
Notes:
1. BUSY is an output in master mode and an input in slave mode.
2. Interrupt: push-pull output and requires no pull-up resistor.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
November 1996
CYPRESS [ CYPRESS SEMICONDUCTOR ]
