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CY62256NLL-70PXC 参数 Datasheet PDF下载

CY62256NLL-70PXC图片预览
型号: CY62256NLL-70PXC
PDF下载: 下载PDF文件 查看货源
内容描述: 256K ( 32K ×8 )静态RAM [256K (32K x 8) Static RAM]
分类和应用: 存储内存集成电路静态存储器光电二极管
文件页数/大小: 13 页 / 710 K
品牌: CYPRESS [ CYPRESS ]
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CY62256N  
Switching Characteristics Over the Operating Range[7]  
CY62256N-55  
CY62256N-70  
Min. Max.  
Parameter  
Read Cycle  
tRC  
Description  
Min.  
Max.  
Unit  
Read Cycle Time  
55  
5
70  
5
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
Data Hold from Address Change  
CE LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low-Z[8]  
OE HIGH to High-Z[8, 9]  
CE LOW to Low-Z[8]  
CE HIGH to High-Z[8, 9]  
CE LOW to Power-up  
CE HIGH to Power-down  
55  
70  
tOHA  
tACE  
55  
25  
70  
35  
tDOE  
tLZOE  
tHZOE  
tLZCE  
tHZCE  
tPU  
5
5
0
5
5
0
20  
20  
55  
25  
25  
70  
tPD  
Write Cycle[10, 11]  
tWC  
Write Cycle Time  
55  
45  
45  
0
70  
60  
60  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tSCE  
tAW  
CE LOW to Write End  
Address Set-up to Write End  
Address Hold from Write End  
Address Set-up to Write Start  
WE Pulse Width  
tHA  
tSA  
0
0
tPWE  
tSD  
40  
25  
0
50  
30  
0
Data Set-up to Write End  
Data Hold from Write End  
WE LOW to High-Z[8, 9]  
WE HIGH to Low-Z[8]  
tHD  
tHZWE  
tLZWE  
20  
25  
5
5
Switching Waveforms  
Read Cycle No. 1[12, 13]  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Notes:  
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
/I and 100-pF load capacitance.  
I
OL OH  
8. At any given temperature and voltage condition, t  
is less than t  
, t  
is less than t  
, and t  
is less than t  
for any given device.  
HZCE  
LZCE HZOE  
LZOE  
HZWE  
LZWE  
9. t  
, t  
, and t  
are specified with C = 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.  
HZOE HZCE  
HZWE L  
10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can  
terminate a Write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the Write.  
11. The minimum Write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of t  
and t  
.
SD  
HZWE  
12. Device is continuously selected. OE, CE = V  
13. WE is HIGH for Read cycle.  
.
IL  
Document #: 001-06511 Rev. *A  
Page 5 of 13  
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