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CY62256NLL-70PXC 参数 Datasheet PDF下载

CY62256NLL-70PXC图片预览
型号: CY62256NLL-70PXC
PDF下载: 下载PDF文件 查看货源
内容描述: 256K ( 32K ×8 )静态RAM [256K (32K x 8) Static RAM]
分类和应用: 存储内存集成电路静态存储器光电二极管
文件页数/大小: 13 页 / 710 K
品牌: CYPRESS [ CYPRESS ]
 浏览型号CY62256NLL-70PXC的Datasheet PDF文件第1页浏览型号CY62256NLL-70PXC的Datasheet PDF文件第3页浏览型号CY62256NLL-70PXC的Datasheet PDF文件第4页浏览型号CY62256NLL-70PXC的Datasheet PDF文件第5页浏览型号CY62256NLL-70PXC的Datasheet PDF文件第6页浏览型号CY62256NLL-70PXC的Datasheet PDF文件第7页浏览型号CY62256NLL-70PXC的Datasheet PDF文件第8页浏览型号CY62256NLL-70PXC的Datasheet PDF文件第9页  
CY62256N  
Product Portfolio  
Power Dissipation  
Operating, ICC  
(mA)  
Standby, ISB2  
VCC Range (V)  
Typ.[2]  
(µA)  
Speed  
(ns)  
Product  
Min.  
Max.  
Typ.[2]  
Max.  
50  
Typ.[2]  
Max.  
50  
5
CY62256NL  
Com’l / Ind’l  
4.5  
5.0  
5.5  
70  
70  
25  
2
CY62256NLL Commercial  
CY62256NLL Industrial  
CY62256NLL Automotive-A  
CY62256NLL Automotive-E  
25  
50  
0.1  
0.1  
0.1  
0.1  
55/70  
55/70  
55  
25  
50  
10  
10  
15  
25  
50  
25  
50  
Pin Configurations  
21  
20  
A
OE  
22  
23  
0
A
1
CE  
I/O  
I/O  
19  
18  
17  
16  
A
24  
7
6
5
4
2
Narrow SOIC  
Top View  
DIP  
Top View  
A
3
25  
26  
I/O  
A
4
TSOP I  
Top View  
(not to scale)  
I/O  
27  
28  
1
WE  
I/O  
15  
14  
13  
3
V
CC  
5
6
A
28  
V
CC  
1
2
3
4
A
28  
V
CC  
5
1
2
3
4
5
GND  
I/O  
A
27 WE  
26  
A
A
2
2
3
27 WE  
26  
A
6
6
12  
11  
I/O  
1
A7  
A
A
A
7
A
7
4
I/O  
4
A
4
0
8
A
10  
9
A
A
25  
3
24  
A
A
5
A
9
14  
25  
3
24  
8
8
A
A
13  
6
7
A
10  
A
A
5
6
A
9
10  
2
5
6
9
10  
2
8
A
12  
A
11  
A
23  
22  
A
A
23  
22  
A
1
1
A
11  
OE  
A
0
CE  
A
11  
OE  
A
0
CE  
7
8
9
10  
11  
12  
13  
14  
7
8
9
10  
11  
12  
13  
14  
21  
20  
19  
18  
17  
A
21  
20  
19  
18  
17  
A
12  
A
12  
8
9
A
7
6
11  
12  
A
A
A
A
10  
13  
13  
13  
A
10  
11  
12  
13  
14  
15  
16  
A
A
A7  
A
5
4
3
14  
A
9
8
A
I/O  
14  
I/O  
I/O  
14  
I/O  
7
7
I/O  
I/O  
1
I/O  
GND  
I/O  
I/O  
I/O  
0
I/O  
I/O  
TSOP I  
Reverse Pinout  
Top View  
6
0
6
0
I/O  
2
I/O  
I/O  
5
I/O  
2
6
1
5
1
A
5
1
28  
I/O  
16 I/O  
15  
I/O  
16 I/O  
15  
2
4
3
2
4
3
V
3
CC  
(not to scale)  
I/O  
GND  
I/O  
GND  
27  
26  
25  
24  
23  
4
5
6
7
WE  
17  
18  
A
4
3
2
1
A
I/O  
19  
20  
A
A
OE  
I/O  
CE  
21  
22  
A
0
Pin Definitions  
Pin Number  
1–10, 21, 23–26  
11–13, 15–19,  
27  
Type  
Input  
Input/Output I/O0–I/O7. Data lines. Used as input or output lines depending on operation  
Description  
A0–A14. Address Inputs  
Input/Control WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is  
conducted  
20  
22  
Input/Control CE. When LOW, selects the chip. When HIGH, deselects the chip  
Input/Control OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins  
behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input  
data pins  
14  
Ground  
GND. Ground for the device  
28  
Power Supply VCC. Power supply for the device  
Note:  
2. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions  
(T = 25°C, V ). Parameters are guaranteed by design and characterization, and not 100% tested.  
A
CC  
Document #: 001-06511 Rev. *A  
Page 2 of 13  
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