CY62187EV30LL-55BAXIT 参数 Datasheet PDF下载

型号：	CY62187EV30LL-55BAXIT
PDF下载：	下载PDF文件查看货源
内容描述：	[Standard SRAM, 4MX16, 55ns, CMOS, PBGA48, 8 X 9.50 MM, 1.40 MM HEIGHT, LEAD FREE, MO-205, FBGA-48]
分类和应用：	存储内存集成电路静态存储器
文件页数/大小：	14 页 / 510 K
品牌：	CYPRESS [ CYPRESS ]

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CY62187EV30 MoBL^®

Truth Table

CE₁

CE₂

X^[27]

BHE

X^[27]

BLE

Inputs Outputs

Mode

Deselect/Power Down

Read

Power

Standby (I_SB

Active (I_CC

X^[27]High Z

)

X^[27]

)

X^[27]

High Z

Data Out (I/O₀–I/O₁₅

)

High Z (I/O₈–I/O₁₅);

Data Out (I/O₀–I/O₇)

Read

)

Data Out (I/O₈–I/O₁₅);

High Z (I/O₀–I/O₇)

Read

Active (I_CC)

Data In (I/O₀–I/O₁₅

)

Write

Active (I_CC

)

High Z (I/O₈–I/O₁₅);

Data In (I/O₀–I/O₇)

Active (I_CC)

Data In (I/O₈–I/O₁₅);

High Z (I/O₀–I/O₇)

Write

Active (I_CC)

High Z

Output Disabled

Active (I_CC

)

Note

27. The ‘X’ (Don’t care) state for the chip enables and byte enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these

pins is not permitted.

Document Number: 001-48998 Rev. *E

Page 10 of 14

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CY62187EV30LL-55BAXIT 参数 Datasheet PDF下载

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