APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Serial Control Registers
NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true
power up. Bytes are set to the values shown only on true power up.
Following the acknowledge of the Address Byte, two additional bytes must be sent:
1) “Command Code “ byte, and
2) “Byte Count” byte.
Although the data (bits) in these two bytes are considered “don’t care”; they must be sent and will be acknowledged.
After the Command Code and the Count bytes have been acknowledged, the below described sequence (Byte 0, Byte 1,
and Byte2) will be valid and acknowledged.
Byte 0: CPU Clock Register (1=Enable, 0=Disable, Default=07)
Byte 1: SDRAM Clock Register (1=Enable, 0=Disable, Default=FF)
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
-
-
-
-
Description
Reserved
Reserved
Reserved
Reserved
Spread spectrum mode
DOT
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
36
37
39
40
42
43
45
46
Description
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
-
26
25
49
USB
CPU2_ITP
Byte 2: PCI Clock Register (1=Enable, 0=Disable, Default=FE)
Byte 3: Reserved Register (Default=00)
Byte 4: Reserved Register (Default=00)
Byte 5: SSCG Control Register (Default=00)
Bit
7
@Pup
Pin#
20
19
18
16
15
13
12
-
Description
PCI7
1
1
1
1
1
1
1
0
6
PCI6
5
PCI5
4
PCI4
Bit
7
@Pup
Pin#
Description
Spread Mode (0=down, 1=center)
Ref. Table 4
Ref. Table 4
Reserved
3
PCI3
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
2
PCI2
6
5
4
1
PCI1
0
Reserved
3
Reserved
2
Reserved
1
Reserved
0
Reserved
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07053 Rev. **
05/03/01
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
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