APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Clock Synchronization and Phase Alignment
This device incorporates IOAPIC clock synchronization. With this feature, the IOAPIC clocks are derived from the CPU
clock. The IOAPIC clock lags the CPU clock by the specified 1.5 to 3.5 nSec. Figure 3 shows the relationship between
the CPU and IOAPIC clocks.
Device Clock Phase Relationships
0nS
10nS
20nS
30nS
40nS
CPU CLOCK
CPU CLOCK
CPU CLOCK
66MHz
2.5nS
100MHz
133MHz
5nS
Sync
7.5nS
5nS
SDRAM CLOCK
100MHz
3V66 CLOCK
PCI CLOCK
66MHz
33MHz
1.5~3.5nS
IOAPIC CLOCK
33MHz
Fig.3
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01
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