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C9812DYB 参数 Datasheet PDF下载

C9812DYB图片预览
型号: C9812DYB
PDF下载: 下载PDF文件 查看货源
内容描述: 低EMI时钟发生器为Intel 810E芯片组的系统 [Low EMI Clock Generator for Intel 810E Chipset Systems]
分类和应用: 时钟发生器
文件页数/大小: 18 页 / 270 K
品牌: CYPRESS [ CYPRESS ]
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APPROVED PRODUCT  
C9812  
Low EMI Clock Generator for Intel 810E Chipset Systems  
AC Parameters  
133 MHz Host  
100 MHz Host  
Symbol  
Parameter  
Units  
Notes  
Min  
7.5  
1.87  
1.67  
0.4  
-
Max  
8.0  
-
Min  
10.0  
3.0  
2.8  
0.4  
-
Max  
10.5  
-
TPeriod  
THIGH  
TLOW  
Tr / Tf  
CPU(0:1) period  
CPU(0:1) high time  
nS  
nS  
nS  
nS  
pS  
pS  
nS  
nS  
nS  
nS  
pS  
nS  
nS  
nS  
nS  
pS  
pS  
nS  
nS  
nS  
nS  
pS  
5, 6, 8  
6,10  
CPU(0:1) low time  
-
-
6, 11  
6, 7  
CPU(0:1) rise and fall times  
CPU0 to CPU1 Skew time  
CPU(0:1) Cycle to Cycle Jitter  
APIC(0:1) period  
1.6  
175  
250  
-
1.6  
175  
250  
-
TSKEW  
TCCJ  
6, 8, 9  
6, 8, 9  
5, 6, 8  
6,10  
-
-
TPeriod  
THIGH  
TLOW  
Tr / Tf  
60.0  
25.5  
25.3  
0.4  
-
60.0  
25.5  
25.3  
0.4  
-
APIC(0:1) high time  
-
-
APIC(0:1) low time  
-
N/S  
1.6  
500  
16.0  
-
6, 11  
6, 7  
APIC(0:1) rise and fall times  
APIC(0:1) Cycle to Cycle Jitter  
3V66-(0:1) period  
1.6  
500  
16.0  
-
TCCJ  
6, 8, 9  
5, 6, 8  
6,10  
TPeriod  
THIGH  
TLOW  
Tr / Tf  
15.0  
5.25  
5.05  
0.4  
-
15.0  
5.25  
5.05  
0.4  
-
3V66-(0:1) high time  
3V66-(0:1) low time  
-
-
6, 11  
6, 7  
3V66-(0:1) rise and fall times  
3V66-0 to 3V66-1 Skew time  
3V66-(0:1) Cycle to Cycle Jitter  
PCI(0:7) period  
1.6  
250  
500  
-
1.6  
250  
500  
-
TSKEW  
TCCJ  
6, 8, 9  
6, 8, 9  
5, 6, 8  
6,10  
-
-
TPeriod  
THIGH  
TLOW  
Tr / Tf  
30.0  
12.0  
12.0  
0.5  
-
30.0  
12.0  
12.0  
0.5  
-
PCI(0:7) period  
-
-
PCI(0:7) low time  
-
-
6, 11  
6, 7  
PCI(0:7) rise and fall times  
2.0  
500  
2.0  
500  
TSKEW  
(Any PCI clock) to (Any PCI clock)  
Skew time  
6, 8, 9  
TCCJ  
PCI(0:7) Cycle to Cycle Jitter  
-
500  
-
500  
pS  
nS  
6, 8, 9  
5, 6, 8  
TPeriod  
48MHz period ( conforms to  
+167ppm max)  
20.8299 20.8333 20.8299 20.8333  
Tr / Tf  
TCCJ  
48MHz rise and fall times  
48MHz Cycle to Cycle Jitter  
REF period  
1.0  
4.0  
500  
71.0  
4.0  
1.0  
4.0  
500  
71.0  
4.0  
nS  
pS  
nS  
nS  
pS  
nS  
nS  
mS  
6, 7  
6, 8, 9  
5, 6, 8  
6, 7  
6, 8  
13  
-
69.8413  
1.0  
-
69.8413  
1.0  
TPeriod  
Tr / Tf  
REF rise and fall times  
TCCJ  
REF Cycle to Cycle Jitter  
-
1000  
10.0  
10.0  
3
-
1000  
10.0  
10.0  
3
tpZL, tpZH  
tpLZ, tpZH  
tstable  
Output enable delay (all outputs)  
Output disable delay (all outputs)  
All clock Stabilization from power-up  
1.0  
1.0  
1.0  
1.0  
13  
12  
Cypress Semiconductor Corporation  
525 Los Coches St.  
Document#: 38-07053 Rev. **  
05/03/01  
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571  
http://www.cypress.com  
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