APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel 810E Chipset Systems
Maximum Ratings
This device contains circuitry to protect the inputs
Maximum Input Voltage Relative to VSS: VSS - 0.3V
Maximum Input Voltage Relative to VDD: VDD + 0.3V
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
Storage Temperature:
Operating Temperature:
Maximum ESD protection
Maximum Power Supply:
-65ºC to + 150ºC
0ºC to +70ºC
2KV
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
5.5V
DC Parameters
Characteristic
Symbol Min
Typ
Max
1.0
Units
Vdc
Vdc
Vdc
Vdc
µA
Conditions
Input Low Voltage
VIL1
VIH1
VIL2
VIH2
IIL
-
-
-
-
-
Note 1
Input High Voltage
2.0
-
-
1.0
-
Input Low Voltage
Note 2
Input High Voltage
2.2
-66
Input Low Current (@VIL = VSS)
Input High Current (@VIL =VDD)
Tri-State leakage Current
Dynamic Supply Current
Dynamic Supply Current
Static Supply Current
Input pin capacitance
Output pin capacitance
Pin capacitance
-5
For internal Pull up resistors,
Notes 1,3
IIH
5
µA
Ioz
-
-
10
280
100
300
5
µA
Idd3.3V
Idd2.5V
Isdd
-
-
mA
mA
µA
Sel2 = Sel1 = Sel0 = 1, Note 4
Sel2 = Sel1 = Sel0 = 1, Note 4
Sel2 = Sel1 = Sel0 = x, Note 4
-
-
-
-
Cin
-
-
pF
Cout
Lpin
-
-
6
pF
-
-
7
nH
Clock Stablization Time
Crystal pin capacitance
Crystal DC Bias Voltage
Crystal Startup time
tstab
Cxtal
VBIAS
Txs
3
32
-
34
-
mSec
pF
Measured from VDD – 3.15 volts
38
0.7Vdd
40
Measured from Pin to Ground. Note 5
0.3Vdd
-
Vdd/2
-
V
From Stable 3.3V power supply.
µS
VDD=VDDS = 3.3V ±5%, VDDC = VDDI = 2.5 ± 5%, TA = 0º to +70ºC
Applicable to input signals: Sel(0:1), PD#
Applicable to Sdata, and Sclk.
Note1:
Note2:
Note3:
Although internal pull-up resistors have a typical value of 250K, this value may vary between 200K and 500K. Internal Pull-down resisters
are typically 70K in value.
Note4:
Note5:
All outputs loaded as per table below.
Although the device will reliably interface with crystals of a 17pF – 20pF CL range, it is optimized to interface with a typical CL = 18pF
crystal specifications.
Clock Name
Max Load (in pF)
CPU, IOAPIC, REF, USB
PCI, SDRAM, 3V66(0,1)
DOT
20
30
15
Table 5.
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07053 Rev. **
05/03/01
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Page 10 of 18
CYPRESS [ CYPRESS ]
