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C9812DYB 参数 Datasheet PDF下载

C9812DYB图片预览
型号: C9812DYB
PDF下载: 下载PDF文件 查看货源
内容描述: 低EMI时钟发生器为Intel 810E芯片组的系统 [Low EMI Clock Generator for Intel 810E Chipset Systems]
分类和应用: 时钟发生器
文件页数/大小: 18 页 / 270 K
品牌: CYPRESS [ CYPRESS ]
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APPROVED PRODUCT  
C9812  
Low EMI Clock Generator for Intel 810E Chipset Systems  
Power on Bi-Directional Pins  
Power Up Condition:  
Pin1 is a Power up bi-directional pin and is used for selecting the host frequency in page 1, table 1. During power-up of  
the device, this pin is in input mode (see Fig 4, below), therefore; it is considered an input select pins internal to the IC.  
After a settling time, the selection data is latch into the internal control register and this pin becomes a clock output.  
VDD RAIL  
POWER SUPPLY  
RAMP  
REF / SEL2  
(Pin 1)  
-
Hi-Z INPUTS  
TOGGLE OUTPUTS  
SELECT DATA IS LATCHED INTO REGISTER THEN PIN BECOMES A REF CLOCK OUTPUT SIGNAL  
Fig.4  
Strapping Resistor Options:  
The power up bi-directional pins have a large value pull-down each (70KΩ), therefore, a selection “0” is the default. If the  
system uses a slow power supply (over 5mS settling time), then it is recommended to use an external Pull-down in  
order to insure a low selection.  
Fig. 5 If a selection “0” is desired, then a jumper is placed on JP1 to a 10Kresistor as implemented as shown in Fig.5.  
Please note the selection resistor (Rdn) is placed before the Damping resistor (Rd) close to the pin.  
JP1  
Vdd  
Jumper  
3
2
1
Rsel  
10K  
IMI C9812  
Rd  
Load  
Bidirectional  
Fig. 5  
70K  
Cypress Semiconductor Corporation  
525 Los Coches St.  
Document#: 38-07053 Rev. **  
05/03/01  
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571  
http://www.cypress.com  
Page 5 of 18  
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