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C9812DYB 参数 Datasheet PDF下载

C9812DYB图片预览
型号: C9812DYB
PDF下载: 下载PDF文件 查看货源
内容描述: 低EMI时钟发生器为Intel 810E芯片组的系统 [Low EMI Clock Generator for Intel 810E Chipset Systems]
分类和应用: 时钟发生器
文件页数/大小: 18 页 / 270 K
品牌: CYPRESS [ CYPRESS ]
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APPROVED PRODUCT  
C9812  
Low EMI Clock Generator for Intel 810E Chipset Systems  
Pin Description  
PIN No.  
Pin Name  
PWR  
VDD  
I/O TYPE  
I/O  
Description  
3.3V 14.318 MHz clock output.  
1
SEL2/REF  
This pin also serves as the select strap (associates with SEL0 &  
1, see app. note page 5) for clock frequencies during power up.  
Refer to Table 1 for detail. This pin has an internal pull-down  
(Typ. 70K).  
3
4
VDD  
VDD  
VDD  
I
O
O
OSC1 14.318MHz Crystal input  
XIN  
XOUT  
PCI0/ICH  
PCI(1..7)  
14.318MHz Crystal output  
3.3V PCI clock outputs  
11, 12, 13,  
15, 16, 18,  
19, 20  
7, 8  
25  
26  
VDD  
VDD  
VDD  
VDD  
O
O
O
I
3.3V Fixed 66.6 MHz clock outputs  
3.3V Fixed 48 MHz clock outputs  
3.3V Fixed 48 MHz clock outputs  
3.3V LVTTL compatible inputs for logic selection. Has an  
internal pull-up (Typ. 250K)  
3V66(0,1)  
USB  
DOT  
28, 29  
SEL(0,1)  
30  
31  
32  
VDD  
VDD  
VDD  
I
I
I
SDATA  
SCLK  
PD#  
I²C compatible SDATA input. Has an internal pull-up (>100K)  
I²C compatible SCLK input. Has an internal pull-up (>100K)  
3.3V LVTTL compatible input. Device enters powerdown mode  
When held LOW. Has an internal pull-up (>100K)  
3.3V output running 100MHz  
34  
VDD  
VDDS  
O
O
DCLK  
SDRAM(7..0)  
36, 37, 39,  
40, 42, 43,  
45, 46  
3.3V output running 100MHz. All SDRAM outputs can be turned  
off through SMBUS.  
49, 50, 52  
VDDC  
VDDI  
-
O
O
2.5V Host bus clock outputs. 66, 100 or 133MHz depending on  
state of SEL(2..0)  
2.5V clock outputs running rising edge synchronous with the  
PCI clock.  
3.3V Power Supply  
CPU(2)_ITP,  
CPU(1,0)  
IOAPIC(1,0)  
54, 55  
2, 9, 10, 21,  
27, 33  
VDD  
22  
23  
51, 53  
5, 6,14, 17,  
24, 35, 41,  
47, 48, 56  
38, 44  
-
-
-
-
Analog circuitry 3.3V Power Supply  
Analog circuitry power supply Ground pins.  
2.5V Power Supply’s  
VDDA  
VSSA  
VDDC, VDDI  
VSS  
-
-
Common Ground pins.  
-
3.3V power support for SDRAM clock output drivers.  
VDDS  
A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin. If these bypass capacitors  
are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces.  
Cypress Semiconductor Corporation  
525 Los Coches St.  
Document#: 38-07053 Rev. **  
05/03/01  
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571  
http://www.cypress.com  
Page 2 of 18  
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