APPROVED PRODUCT
C9812
Low EMI Clock Generator for Intel
810E Chipset Systems
Product Features
•
•
•
•
•
•
•
•
•
•
•
•
Intel’s 810E clock solution
3 copies of CPU Clock (CPU[0:1] and CPU_ITP)
9 copies of SDRAM Clock (SDRAM[0:7] and DCLK)
8 copies of PCI Clock
2 copies of 3V66 Clock
2 copies of APIC Clock, synchronous to PCI Clock
1 REF Clock
1 USB Clock (Non SSC)
1 DOT Clock (Non SSC)
Power Down Feature
Spread Spectrum Support
SMBUS Support for turning off unused clocks
Frequency Table (MHz)
SEL2
X
X
0
0
1
SEL1
0
0
1
1
1
SEL0
0
1
0
1
X
CPU
Tristate
66.6
100
133.3
Table 1
SDRAM
Tristate
100
100
100
PCI
Tristate
33.3
33.3
33.3
Test mode (see table2)
Note: The following clocks remain fixed frequencies
except in Test Mode.
3V66=66.6MHz, USB/DOT=48MHz, REF=14.318MHz
and IOAPIC=33.3MHz.
Block Diagram
XIN
36pF
300K
36pF
XOUT
1
VDD
REF / SE L2
Pin Configuration
SEL2/REF
VDD
XIN
XOUT
VSS
VSS
3V660
3V661
VDD
VDD
PCI0_ICH
PCI1
PCI2
VSS
PCI3
PCI4
VSS
PCI5
PCI6
PCI7
VDD
VDDA
VSSA
VSS
USB
DOT
VDD
SEL0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VSS
IOAPIC0
IOAPIC1
VDDI
CPU0
VDDC
CPU1
CPU2_ITP
VSS
VSS
SDRAM0
SDRAM1
VDDS
SDRAM2
SDRAM3
VSS
SDRAM4
SDRAM5
VDDS
SDRAM6
SDRAM7
VSS
DCLK
VDD
PD#
SCLK
SDATA
SEL1
VDDI
s2
Rin
VDDC
SCLK
SDATA
i2c-clk
i2c-data
cpu
3
CPU(0:2)
ioapic
2
IOAP IC(0:1)
VDDS
VDD
SEL1
SEL0
PD#
VDD
sdram
s1
9
VDD
SDRA M(0:7), DC LK
C
9
8
1
2
s0
pwr_dwn#
66m
2
VDD
3V66(0:1)
pci
PLL1
Rin
PD#
48
8
VDD
1
VDD
1
PCI(0:7)
DOT
USB
i2c-clk
i2c-data
PLL2
Fig.1
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07053 Rev. **
05/03/01
Page 1 of 18
CYPRESS [ CYPRESS SEMICONDUCTOR ]
