PRELIMINARY
CYW54907
15.3 CLDO
Table 35. CLDO Specifications
Specification
Notes
Min. Typ. Max.
Units
Input supply voltage, Vin
Min. = 1.2 + 0.15V = 1.35V dropout voltage requirement
must be met under maximum load.
1.3
1.35
1.5
V
Output current
–
0.2
0.95
–
–
1.2
–
350
1.26
150
+4
–
mA
V
Output voltage, Vo
Dropout voltage
Programmable in 10 mV steps. Default = 1.2.V.
At max. load.
mV
%
Output voltage DC accuracy
Quiescent current
Includes line/load regulation.
No load.
–4
–
–
26
2.48
–
µA
200 mA load.
–
–
mA
mV/V
mV/mA
µA
Line regulation
Load regulation
Leakage current
V
in from (Vo + 0.15V) to 1.5V, maximum load.
–
5
Load from 1 mA to 300 mA.
Power down.
–
0.02 0.05
–
10
2
40
6
Bypass mode.
–
µA
PSRR
@1 kHz, Vin ≥ 1.35V, Co = 4.7 µF.
20
–
–
dB
Start-up time of PMU
VIO up and steady. Time from the REG_ON rising edge to
the CLDO reaching 1.2V.
–
700
µs
LDO turn-on time
LDO turn-on time when the rest of the chip is up.
Total ESR: 5 mΩ–240 mΩ.
–
3.76a
–
140
4.7
1
180
–
µs
µF
µF
External output capacitor, Co
External input capacitor
Only use an external input capacitor at the LDO_VDD1P5
pin if it is not supplied from the CBUCK output.
2.2
a. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and
aging.
Document Number: 002-19312 Rev. *C
Page 67 of 95
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