BCM43907 Preliminary Data Sheet
SDIO Interface Timing
Device Output Timing
SDIO device output timing in the SDR modes with clock rates up to 50 MHz is shown by the combination of
Figure 28 and Table 49.
Figure 28: SDIO Bus Output Timing (SDR Modes up to 50 MHz)
tCLK
SDIO_CLK
tODLY
tOH
CMD input
DAT[3:0] input
Table 49: SDIO Bus Output Timing Parameters (SDR Modes up to 50 MHz)
Symbol
Minimum
Maximum
Unit
ns
Comments
t ≥ 20 ns C = 40 pF
CLK
t
t
–
14.0
–
ODLY
OH
L
1.5
ns
Hold time at the t
(min.) C = 15 pF
ODLY L
Broadcom®
March 12, 2016 • 43907-DS104-R
Page 109
BROADCOM CONFIDENTIAL