BCM43907 Preliminary Data Sheet
S/PDIF Interface Timing
Table 50 provides the S/PDIF biphase mark code timing parameters (to be used in conjunction with Figure 30
on page 110).
Table 50: SPDIF Biphase Mark Code Timing Parameters
Parameter
Symbol
Minimum
Maximum
Unit
ns
Comments
–
–
t
t
40
–
–
192 kHz sample rate
–
CLK
, t
0.3 × t
ns
CR CF
CLK
Duty cycle
–
30
70
%
–
Table 51 provides the S/PDIF biphase mark code sample rate and receiver clock frequency.
Table 51: SPDIF Biphase Mark Code Sample Rate and Receiver Clock Frequency
Parameter
Symbol
Minimum
Maximum
Unit
Comments
Sampling
frequency
f
–
192
kHz
192 kHz sample rate maximum.
S
Component
clock
frequency
f
–
25
MHz
Typical is 128 × f max is 192 × f .
S, S
CLOCK
Clock is 2× the desired data rate or
2 × 192 kHz × 64 = 24.576 MHz.
Broadcom®
March 12, 2016 • 43907-DS104-R
Page 111
BROADCOM CONFIDENTIAL
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