SPI Flash Timing
BCM43907 Preliminary Data Sheet
Write-Register Timing
Figure 32 shows the SPI flash extended and quad write-register timing.
Note: Regarding Figure 32:
1. All write-register commands except Write Lock Register are supported.
2. The waveform must be extended for each protocol: to 23 for extended and five for quad.
3. A Write Nonvolatile Configuration Register operation requires data being sent starting from the least significant byte.
Figure 32: SPI Flash Write-Register Timing
0
7
8
9
10
11
12
13
14
15
Extended
C
LSB
LSB
DQ0
Command
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
MSB
MSB
0
1
2
3
Quad
C
LSB
LSB
DQ[3:0]
Command
DIN
DIN
DIN
MSB
MSB
Broadcom®
March 12, 2016 • 43907-DS104-R
Page 113
BROADCOM CONFIDENTIAL
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