BCM43907 Preliminary Data Sheet
SDIO Interface Timing
SDIO Interface Timing
SDIO Default-Speed Mode Timing
SDIO default-speed (DS) mode timing is shown by the combination of Figure 24 and Table 45.
Figure 24: SDIO Bus Timing (Default-Speed Mode)
fPP
tWL
tWH
SDIO_CLK
tTHL
tTLH
tIH
tISU
Input
Output
tODLY
tODLY
(max)
(min)
Table 45: SDIO Bus Timinga Parameters (Default-Speed Mode)
Parameter
Symbol
Minimum Typical
Maximum Unit
SDIO_CLK or CLK—All values are referred to minimum VIH and maximum VILb
Frequency – Data Transfer mode
Frequency – Identification mode
Clock low time
fPP
0
–
–
–
–
–
–
25
400
–
MHz
kHz
ns
fOD
tWL
tWH
tTLH
tTHL
0
10
10
–
Clock high time
–
ns
Clock rise time
10
10
ns
Clock low time
–
ns
Inputs: CMD, DAT (referenced to CLK)
Input setup time
Input hold time
tISU
tIH
5
5
–
–
–
–
ns
ns
Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer mode
Output delay time – Identification mode
tODLY
tODLY
0
0
–
–
14
50
ns
ns
a. Timing is based on CL 40 pF load on CMD (command) and DAT (data) lines.
b. Min. (Vih) = 0.7 × VDDIO and max. (Vil) = 0.2 × VDDIO.
Broadcom®
March 12, 2016 • 43907-DS104-R
Page 105
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