SPI Flash Timing
BCM43907 Preliminary Data Sheet
SPI Flash Timing
Read-Register Timing
Figure 31 shows the SPI flash extended and quad read-register timing.
Note: Regarding Figure 31: All Read Register commands except Read Lock Register are supported. A Read Nonvolatile Configuration
Register operation will output data starting from the least significant byte.
Figure 31: SPI Flash Read-Register Timing
0
7
8
9
10
11
12
13
14
15
Extended
C
LSB
DQ0
DQ1
Command
High-Z
MSB
LSB
DOUT
MSB
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
0
1
2
3
Quad
C
LSB
LSB
DOUT
DQ[3:0]
Command
DOUT
MSB
DOUT
Don’t care
MSB
Broadcom®
March 12, 2016 • 43907-DS104-R
Page 112
BROADCOM CONFIDENTIAL
CYPRESS [ CYPRESS ]
