BCM43907 Preliminary Data Sheet
SDIO Interface Timing
SDIO High-Speed Mode Timing
SDIO high-speed (HS) mode timing is shown by the combination of Figure 25 and Table 46.
Figure 25: SDIO Bus Timing (High-Speed Mode)
fPP
tWL
tWH
50% VDD
SDIO_CLK
tTHL
tTLH
tIH
tISU
Input
Output
tODLY
tOH
Table 46: SDIO Bus Timinga Parameters (High-Speed Mode)
Parameter
Symbol
Minimum Typical
Maximum Unit
SDIO_CLK or CLK—All values are referred to minimum VIH and maximum VILb
Frequency – Data Transfer Mode
Frequency – Identification Mode
Clock low time
fPP
0
0
7
7
–
–
–
–
–
–
–
–
50
400
–
MHz
kHz
ns
fOD
tWL
tWH
tTLH
tTHL
Clock high time
–
ns
Clock rise time
3
ns
Clock low time
3
ns
Inputs: CMD, DAT (referenced to CLK)
Input setup time
Input hold time
tISU
tIH
6
2
–
–
–
–
ns
ns
Outputs: CMD, DAT (referenced to CLK)
Output delay time – Data Transfer Mode
Output hold time
tODLY
tOH
–
–
–
–
14
–
ns
ns
pF
2.5
–
Total system capacitance (each line)
CL
40
a. Timing is based on CL 40 pF load on CMD (command) and DAT (data) lines.
b. Min. (Vih) = 0.7 × VDDIO and max. (Vil) = 0.2 × VDDIO.
Broadcom®
March 12, 2016 • 43907-DS104-R
Page 106
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