CYW43362
go immediately from enabled to disabled. The terms enable sequence and disable sequence refer to either the immediate transition
or the timer load-decrement sequence.
During each clock cycle, the PMU sequencer performs the following actions:
1. Computes the required resource set based on requests and the resource dependency table.
2. Decrements all timers whose values are nonzero. If a timer reaches 0, the PMU clears the ResourcePending bit for the resource
and inverts the ResourceState bit.
3. Compares the request with the current resource status and determines which resources must be enabled or disabled.
4. Initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered-up dependents.
5. Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled.
2.5 Low-Power Shutdown
The CYW43362 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other device
in the system, remain operational. When WLAN is not needed, the WLAN core can be put in reset by asserting WL_RST_N (logic
LOW). VDDIO_RF and VDDIO remain powered while VIO and VBAT are both present, allowing the CYW43362 to be effectively off
while keeping the I/O pins powered. During a low-power shut-down state, provided VIO continues to be supplied to the CYW43362,
most outputs are tristated and most inputs are disabled. Input voltages must remain within the limits defined for normal operation.
This is done to prevent current paths or create loading on any digital signals in the system, enabling the CYW43362 to be a fully inte-
grated embedded device that takes full advantage of the lowest power-saving modes.
Two signals on the CYW43362, the system clock input (OSCIN) and sleep clock input (EXT_SLEEP_CLK), are designed to be high-
impedance inputs that do not load down the driving signal even if the CYW43362 does not have VDDIO power applied to it. When
the CYW43362 is powered on from this state, it is the same as a normal power-up, and the device does not contain any information
about its state from before it was powered down.
2.6 CBUCK Regulator Features
The CBUCK regulator has several features that help make the CYW43362 ideal for mobile devices. First, the regulator uses 3.2
MHz as its PWM switching frequency for Buck regulation. This high frequency allows the use of small passive components for the
switcher's external circuit, thereby saving PCB space in the design. In addition, the CBUCK regulator has three modes of operation:
PWM mode for low-ripple output and for fast transient response and extended load ranges, Burst Mode for lower currents, and Low
Power Burst Mode for higher efficiency when the load current is very low (Low Power Burst mode is not available for external
devices).
The CBUCK supports external SMPS request to allow flexibility of supplying 1.8V to CYW43362, BCM2076, and other external
devices when EXT_SMPS_REQ is asserted high. It also supports low ripple PWM mode (7 mVpp typical) for noise-sensitive appli-
cations when EXT_PWM_REQ is asserted high. A 100 µs wait/settling time from the assertion of EXT_PWM_REQ high before
increasing the load current allows the internal integrator precharging to complete. This is not a requirement, but is preferred.
Table 2 lists the mode the CBUCK operates in (Burst or PWM), based on various external control signals and internal CBUCK mode
register settings.
Table 2. CBUCK Operating Mode Selection
Internal CBUCK Mode
WL_RST_L
EXT_SMPS_REQ
EXT_PWM_REQ
Required
CBUCK Mode
0
0
0
1
1
1
1
1
0
1
1
0
0
1
1
1
X
0
1
X
X
0
0
1
X
Off
X
BURST
PWM
X
BURST
PWM
BURST
PWM
X
BURST
PWM
BURST
PWM
PWM
Document No. 002-14779 Rev. *G
Page 9 of 60
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