CYW43362
For detailed CBUCK performance specifications, see Core Buck Regulator on page 48.
3. Frequency References
An external crystal is used for generating all radio frequencies and normal operation clocking. As an alternative, an external fre-
quency reference driven by a temperature-compensated crystal oscillator (TCXO) signal may be used. No software settings are
required to differentiate between the two. In addition, a low-power oscillator (LPO) is provided for lower power mode timing.
3.1 Crystal Interface and Clock Generation
The CYW43362 can use an external crystal to provide a frequency reference. The recommended configuration for the crystal oscil-
lator, including all external components, is shown in Figure 4. Consult the reference schematics for the latest configuration.
Figure 4. Recommended Oscillator Configuration
C
OSCIN
12 – 27 pF
C
OSCOUT
R
12 – 27 pF
Note: Resistor value determined by crystal drive
level. See reference schematics for details.
The CYW43362 uses a fractional-N synthesizer to generate the radio frequencies, clocks, and data/packet timing. This enables it to
operate using numerous frequency references. This may either be an external source such as a TCXO or a crystal interfaced directly
to the CYW43362.
The default frequency reference setting is a 26 MHz crystal or TCXO. The signal requirements and characteristics for the crystal
interface are shown in Table 3 on page 11.
Note: Although the fractional-N synthesizer can support many reference frequencies, frequencies other than the default require
support to be added in the driver, plus additional extensive system testing. Contact Cypress for further details.
3.2 TCXO
As an alternative to a crystal, an external precision TCXO can be used as the frequency reference, provided that it meets the Phase
Noise requirements listed in Table 3 on page 11. When the clock is provided by an external TCXO, there are two possible connection
methods, as shown in Figure 5 and Figure 6:
1. If the TCXO is dedicated to driving the CYW43362, it should be connected to the OSC_IN pin through an external 1000 pF
coupling capacitor, as shown in Figure 5. The internal clock buffer connected to this pin will be turned OFF when the CYW43362
goes into sleep mode. When the clock buffer turns ON and OFF, there will be a small impedance variation up to ±15%. Power
must be supplied to the WRF_XTAL_VDD1P2 pin.
2. An alternative is to DC-couple the TCXO to the WRF_TCXO_IN pin, as shown in Figure 6. Use this method when the same TCXO
is shared with other devices and a change in the input impedance is not acceptable because it may cause a frequency shift that
cannot be tolerated by the other device sharing the TCXO. This pin is connected to a clock buffer powered from
WRF_TCXO_VDD3P3. If the power supply to this buffer is always on (even in sleep mode), the clock buffer is always on, thereby
ensuring a constant input impedance in all states of the device. The maximum current drawn from WRF_TCXO_VDD3P3 is
approximately 500 µA.
Document No. 002-14779 Rev. *G
Page 10 of 60
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