CYW43362
Table 4. External 32.768 kHz Low-Power Oscillator Specifications
Specification
Typical
Symbol
Parameter
Condition/Notes
Minimum
Maximum
Units
Fr
Frequency
–
–
32768
–
Hz
f/fr
Frequency tolerance
At 25°C
–30
–150
–220
30
–
–
–
–
–
–
–
–
–
+30
+40
+40
70
ppm
–20°C <Ta< +70°C
–30°C <Ta< +85°C
Duty cycle
–
–
%
V
Vol
Voh
Tr/Tf
–
Output low voltage
Output high voltage
Rise and fall time
Signal type
–
0
0.2
Vio
100
–
–
0.7 Vio
–
V
–
ns
–
Digital
–
–
Clock jitter
Integrated over 300 Hz to
15 kHz
–
30
ns
–
–
Input impedance
Input amplitude
Resistive
10
–
–
–
–
–
MΩ
pF
V
Capacitive
2
Fail safe, 3.3V digital I/O
–
3.63
4. WLAN System Interfaces
4.1 SDIO v2.0
The CYW43362 WLAN section supports SDIO version 2.0. for both 1-bit (25 Mbps), 4-bit modes (100 Mbps), and high speed 4-bit
(50 MHz clocks—200 Mbps). It has the ability to map the interrupt signal on a GPIO pin. This out-of-band interrupt signal notifies the
host when the WLAN device wants to turn on the SDIO interface. The ability to force control of the gated clocks from within the
WLAN chip is also provided.
SDIO mode is enabled using the strapping option pins. See Table 11 on page 40 for details.
Three functions are supported:
■
■
Function 0 Standard SDIO function (Max BlockSize/ByteCount = 32B)
Function 1 Backplane Function to access the internal System On Chip (SOC) address space (Max BlockSize/ByteCount =
64B)
■
Function 2 WLAN Function for efficient WLAN packet transfer through DMA (Max BlockSize/ByteCount = 512B)
4.1.1 SDIO Pin Descriptions
Table 5. SDIO Pin Descriptions
SD 4-Bit Mode
SD 1-Bit Mode
gSPI Mode
DATA0
DATA1
DATA2
DATA3
CLK
Data line 0
DATA
IRQ
NC
Data line
DO
IRQ
NC
Data output
Data line 1 or Interrupt
Data line 2
Interrupt
Interrupt
Not used
Card select
Clock
Not used
Not used
Clock
Data line 3
NC
CS
Clock
CLK
CMD
SCLK
DI
CMD
Command line
Command line
Data input
Document No. 002-14779 Rev. *G
Page 13 of 60
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