CYW43362
Table 3. Crystal Oscillator and External Clock Requirements and Performance (Cont.)
External Frequency
Crystal
Reference
Parameter
Conditions/Notes
Min
Typ
Max
Min
Typ
Max
Units
%
Duty cycle
26 MHz clock
40
50
–
60
Phase Noisee, f
(IEEE 802.11 b/g)
26 MHz clock at 1 kHz offset
26 MHz clock at 10 kHz offset
26 MHz clock at 100 kHz offset
26 MHz clock at 1 MHz offset
26 MHz clock at 1 kHz offset
26 MHz clock at 10 kHz offset
26 MHz clock at 100 kHz offset
26 MHz clock at 1 MHz offset
–
–
–
–
–
–
–
–
–119
–129
–134
–139
–124
–134
–139
–144
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
–
–
–
Phase Noisee, f
(IEEE 802.11n, 2.4 GHz)
–
–
–
–
a. The frequency step size is approximately 80 Hz. The CYW43362 does not auto-detect the reference clock frequency; the frequency is specified
in the software/NVRAM file.
b. The internal clock buffer connected to this pin will be turned off when the CYW43362 goes into Sleep mode. When the clock buffer turns on and
off, there will be a small impedance variation up to ±15%.
c. This input has an internal DC blocking capacitor, so do not include an external DC blocking capacitor.
d. The maximum allowable voltage swing for the WRF_TCXO_IN input is equal to the WRF_TCX0_VDD3P3 supply voltage range, which is 1.7V
to 3.3V.
e. For a clock reference other than 26 MHz, 20 × log10(f/26) dB should be added to the limits, where f = the reference clock frequency in MHz.
f.
If the selected clock has a flat phase-noise response above 100 kHz, then it is acceptable to subtract 1 dB from all 1 kHz, 10 kHz, and 100 kHz
values shown, and ignore the 1 MHz requirement.
3.3 External 32.768 kHz Low-Power Oscillator
The CYW43362 uses a secondary low-frequency sleep clock for low-power mode timing. Either the internal low-precision LPO or an
external 32.768 kHz precision oscillator is required. The internal LPO frequency range is approximately 33 kHz ± 30% over process,
voltage, and temperature, which is adequate for some applications. However, one trade-off caused by this wide LPO tolerance is a
small current consumption increase during power save mode that is incurred by the need to wake up earlier to avoid missing bea-
cons.
Whenever possible, the preferred approach is to use a precision external 32.768 kHz clock that meets the requirements listed in
Table 4.
Note: The CYW43362 will auto-detect the LPO clock. If it senses a clock on the EXT_SLEEP_CLK pin, it will use that clock. If it
doesn't sense a clock, it will use its own internal LPO.
■
To use the internal LPO: Tie EXT_SLEEP_CLK to ground. Do not leave this pin floating. To use an external LPO: Con-
nect the external 32.768 kHz clock to EXT_SLEEP_CLK.
Document No. 002-14779 Rev. *G
Page 12 of 60
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