CYW43362
2. Power Supplies and Power Management
2.1 WLAN Power Management
The CYW43362 has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the
chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage cur-
rent and supply voltages. Additionally, the CYW43362 integrated RAM is a low-leakage memory with dynamic clock control. The
dominant supply current consumed by the RAM is leakage current only.
Additionally, the CYW43362 includes an advanced WLAN power management unit (PMU) sequencer. The PMU sequencer provides
significant power savings by putting the CYW43362 into various power management states appropriate to the current environment
and activities that are being performed. The power management unit enables and disables internal regulators, switches, and other
blocks based on a computation of the required resources and a table that describes the relationship between resources and the time
needed to enable and disable them. Power-up sequences are fully programmable. Configurable, free-running counters, which run
on the 32.768 kHz low-power oscillator (LPO) sleep clock in the PMU sequencer, are used to turn individual regulators and power
switches on and off. Clock speeds are dynamically changed, or gated off, as appropriate for the current mode. Slower clock speeds
are used wherever possible.
The CYW43362 power states are described as follows:
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Active mode—All components in the CYW43362 are powered up and fully functional with active carrier sensing and frame
transmission and receiving. All required regulators are enabled and put in the most efficient mode (PWM or Burst) based on
the load current. Clock speeds are dynamically adjusted by the PMU sequencer.
■
Sleep mode—The radio, AFE, PLLs, and the crystal oscillator are powered down. The rest of the CYW43362 remains pow-
ered up in an IDLE state. All main clocks are shut down. The 32.768-kHz LPO sleep clock is available only for the PMU
sequencer. This condition is necessary to allow the PMU sequencer to wake up the chip and transition to Active mode. In
Sleep mode, the primary power consumed is due to leakage current.
■
■
Power-down modes—The CYW43362 has a full power-down mode and a low-power shutdown mode. A full power-down
occurs when there is no VIO voltage, and WL_RST_N and EXT_SMPRS_REQ are low. A low-power shutdown occurs
when VIO is present, and WL_RST_N and EXT_SMPRS_REQ are low. In low-power shutdown, only the band gap and
LDO3P3 are on. Both power-down modes are exited when the host asserts either WL_RST_N or EXT_SMPS_REQ high.
External mode—In this mode, the following are true:
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❐
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The assertion of EXT_SMPS_REQ turns only the Core Buck (CBUCK) regulator on.
The WLAN is in reset (WL_RST_N = low).
The state of LDO3P3 and the band gap are dependent on VBAT and VIO.
2.2 Power Supply Topology
The CYW43362 contains a Power Management Unit (PMU), a buck-mode switching regulator, and three low noise LDOs. These
integrated regulators simplify power supply design in WLAN embedded designs. All regulator inputs and outputs are brought out to
pins on the CYW43362, providing system designers with the flexibility to choose which of the CYW43362 integrated regulators to
use. One option is to supply the PMU from a single, variable power supply, VBAT, which can range from 2.3V to 4.8V. Using this
option, all of the required voltages are provided by CYW43362 regulators except for a low current rail, VIO, which must be provided
by the host to power the I/O signal buffers when the chip is out of reset.
Alternately, if specific rails such as 3.3V, 1.8V, and 1.2V already exist in the system, appropriate regulators in the CYW43362 can be
bypassed, thereby reducing the cost and board space associated with external regulator components such as inductors and large
capacitors.
The CBUCK and CLDO get powered whenever the reset signal is deasserted. The CBUCK regulator can be turned ON by asserting
EXT_SMPS_REQ high. Asserting EXT_PWM_REQ high will set CBUCK to PWM mode. Driving EXT_PWM_REQ low will put
CBUCK in Burst mode. Optionally, LNLDO may also be powered. All regulators are powered down only when the reset signal is
asserted.
Document No. 002-14779 Rev. *G
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