CYW43362
Figure 15. WLAN Boot-Up Sequence
32.768 kHz
LPO Sleep
Clock
Ramp time from 0V to 4.3V > 40 µs
0.6V
VBAT
VDDIO
> 2 Sleep Clock cycles
WL_RST_N/
EXT_SMPS_REQ
< 1.5 ms
< 3 ms
VDDC
(from internal PMU)
Internal POR
After a fixed delay following internal POR going high,
the device responds to host F0 (address 0x14) reads.
< 50 ms
Device requests for reference clock
1
1
8
ms
After 8 ms the reference clock
is assumed to be up. Access to
PLL registers is possible.
SPI Host Interaction:
Host polls F0 (address 0x14) until it reads
a predefined pattern.
Host sets wake‐up‐wlan bit
1
and waits 8 ms , the
maximum time for
1
After 8 ms, the host
reference clock availability.
programs the PLL registers to
set the crystal frequency
Chip‐active interrupt is asserted after the PLL locks
WL_IRQ
Host downloads
code.
1
This wait time is programmable in sleep clock increments from 1 to 255 (30 us to 8 ms)
4.3 External Coexistence Interface
To manage wireless medium sharing for optimal performance, an external coexistence interface is provided that enables signaling
between the CYW43362 and one or two external collocated wireless devices such as Bluetooth and/or WiMax. Note that three of the
External Coexistence Interface pins are multiplexed with GPIOs. By default, the pins are BT_COEX pins. Through software they can
be changed to GPIOs. The fourth BT_COEX signal is also multiplexed with a GPIO, but this one is a GPIO by default and can be
changed via software to be BTCX_FREQ. See Pinout and Signal Descriptions on page 32 for more details.
Document No. 002-14779 Rev. *G
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