CYW43362
Figure 14. gSPI Signal Timing with Status (Response Delay = 0)
cs
Write
sclk
mosi
miso
CC3311
CC11 CC00 DD3311
DD11 DD00
SS3311
SS11 SS00
Status 32 bits
Command 32 bits
Write Data 16*n bits
Write-Read
cs
sclk
mosi
miso
CC3311
CC00
SS3311
SS00
DD3311
DD11 DD00
Read Data 16*n bits
Status 32 bits
Command 32 bits
Read
cs
sclk
mosi
miso
CC3311
CC00
SS3311
Status 32 bits
SS00
DD3311
DD11 DD00
Command 32 bits
Read Data 16*n bits
Table 6. gSPI Status Field Details
Bit Name
Description
The requested read data is not available.
0
Data not available
Underflow
1
FIFO underflow occurred due to current (F2, F3) read command.
FIFO overflow occurred due to current (F1, F2, F3) write command.
F2 channel interrupt
2
Overflow
3
F2 interrupt
5
F2 RX Ready
Reserved
F2 FIFO is ready to receive data (FIFO empty).
–
7
8
F2 Packet Available
F2 Packet Length
Packet is available/ready in F2 TX FIFO.
Length of packet available in F2 FIFO
9:19
4.2.2 gSPI Host-Device Handshake
To initiate communication through the gSPI after power-up, the host needs to bring up the WLAN/Chip by writing to the wake-up
WLAN register bit. Writing a 1 to this bit will start up the necessary crystals and PLLs so that the CYW43362 is ready for data trans-
fer. The device can signal an interrupt to the host indicating that the device is awake and ready. This procedure also needs to be fol-
lowed for waking up the device in sleep mode. The device can interrupt the host using the WLAN IRQ line whenever it has any
information to pass to the host. On getting an interrupt, the host needs to read the interrupt and/or status register to determine the
cause of interrupt and then take necessary actions.
Document No. 002-14779 Rev. *G
Page 19 of 60
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