CYW43362
Table 7. gSPI Registers (Cont.)
Address
Register
Bit
Access
R/U
Default
Description
x000E,
x000F
F2 info register
0
1
1
0
F2 enabled
R
F2 ready for data transfer
F2 max packet size
15:2
31:0
R/U
R
14'h800
x0014 to
x0017
Test–Read only
register
32'hFEEDBEA This register contains a predefined pattern, which the host can
read and determine if the gSPI interface is working properly.
D
x0018 to
x001B
Test–R/W register
31:0
7:0
R/W/U
R/W
32'h00000000 This is a dummy register where the host can write some
pattern and read it back to determine if the gSPI interface is
working properly.
x001C to
x001F
Response delay
registers
0x1D=4, other Individual response delays for F0, F1, F2, and F3. The value
registers = 0
of the registers is the number of byte delays that are
introduced before data is shifted out of the gSPI interface
during host reads.
Figure 15 on page 22 shows the WLAN boot-up sequence from power-up to firmware download, including the initial device power-
on reset (POR) evoked by the WL_RST_N signal. After initial power-up, the WL_RST_N signal can be held low to disable the
CYW43362 or pulsed low to induce a subsequent reset.
Note: The CYW43362 has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 3 ms after VDD
and VDDIO have both passed the 0.6V threshold.
Document No. 002-14779 Rev. *G
Page 21 of 60
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