CYW43362
4.2.3 Boot-Up Sequence
After power-up, the gSPI host needs to wait 50 ms for the device to be out of reset. For this, the host needs to poll with a read com-
mand to F0 addr 0x14. Address 0x14 contains a predefined bit pattern. As soon as the host gets a response back with the correct
register content, it implies that the device has powered up and is out of reset. After that, the host needs to set the wakeup-WLAN bit
(F0 reg 0x00 bit 7). Wakeup-WLAN turns the PLL on; however, the PLL doesn't lock until the host programs the PLL registers to set
the crystal frequency.
For the first time after power-up, the host needs to wait for the availability of low-power clock inside the device. Once that is avail-
able, the host needs to write to a PMU register to set the crystal frequency. This will turn on the PLL. After the PLL is locked, the chi-
pActive interrupt is issued to the host. This indicates device awake/ready status. See Table 7 for information on gSPI registers.
In Table 7, the following notation is used for register access:
■
■
■
R: Readable from host and CPU
W: Writable from host
U: Writable from CPU
Table 7. gSPI Registers
Address
Register
Bit
Access
Default
Description
x0000
Word length
0
1
4
R/W/U
0
0
1
0: 16-bit word length
1: 32-bit word length
Endianess
R/W/U
R/W/U
0: Little Endian
1: Big Endian
High-speed mode
0: Normal mode. Sample on SPICLK rising edge, output on
falling edge.
1: High-speed mode. Sample and output on rising edge of
SPICLK (default).
Interrupt polarity
Wake-up
5
7
R/W/U
R/W
1
0
0: Interrupt active polarity is low.
1: Interrupt active polarity is high (default).
Awrite of 1 will denote wake-up command from host to device.
This will be followed by a F2 Interrupt from gSPI device to
host, indicating device awake status.
x0002
Status enable
0
1
R/W
R/W
1
0
0: no status sent to host after read/write
1: status sent to host after read/write
Interrupt with status
0: do not interrupt if status is sent
1: interrupt host even if status is sent
x0003
x0004
Reserved
–
0
–
–
0
–
Interrupt register
R/W
Requested data not available; Cleared by writing a 1 to this
location
1
2
5
6
7
5
6
7
R
0
0
0
0
0
0
0
0
F2/F3 FIFO underflow due to last read
F2/F3 FIFO overflow due to last write
F2 packet available
R
R
R
F3 packet available
R
F1 overflow due to last write
F1 Interrupt
x0005
Interrupt register
R
R
F2 Interrupt
R
F3 Interrupt
x0006,
x0007
Interrupt enable
register
15:0
R/W/U
16'hE0E7
Particular Interrupt is enabled if a corresponding bit is set
x0008 to
x000B
Status register
31:0
R
32'h0000
Same as status bit definitions
x000C,
x000D
F1 info register
0
R
1
F1 enabled
1
R
0
F1 ready for data transfer
F1 max packet size
13:2
R/U
12'h40
Document No. 002-14779 Rev. *G
Page 20 of 60
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